On each active clock edge, a flip-flop needs D stable in a small window around that edge.
Definitions
| Constraint | Meaning |
|---|---|
| Setup | D must be stable before the capture edge by (t_{su}) |
| Hold | D must remain stable after the capture edge by (t_h) |
Path delay from launch FF → combo → capture FF must land inside the period (setup) without being too fast (hold).
Intuition with one period
For a simple single-cycle path:
[ t_{clk\to q} + t_{combo} + t_{su} < T_{clk} - t_{skew} ]
Hold is often threatened by very short paths (little combo) and clock skew — physical design inserts delay or uses suitable cells; in RTL you avoid pathological “clock as data” tricks.
What RTL authors control
- Logic depth between flops (pipeline if too deep).
- Multi-cycle paths — only with explicit false-path / MCP constraints in a real STA flow.
- Not relying on “it worked in sim” — zero-delay or unit-delay sim hides setup.
Symptoms of timing failure
- Rare corruption at high clock rates / cold/hot corners
- Works in behavioral sim, fails on FPGA at speed
- Intermittent protocol errors under load
Practical habits
- Keep control FSMs shallow; pipeline wide arithmetic.
- Register block outputs at module boundaries when timing is tight.
- Don’t create combo loops.
- Treat async inputs as CDC, not as synchronous
D.