Clock-Domain Crossing

IP blocks

• 1-Bit Handshake CDC Bridge verilogsimsyn

  A robust 1-bit handshake protocol for crossing clock domains ensuring reliable data transfer without loss.

• 3-Stage Asynchronous Reset Synchronizer verilogsimsyn

  Synchronizes an asynchronous active-low reset signal to a synchronous clock domain using a 3-stage flip-flop chain to minimize metastability.

• 4-Bit Bus Synchronizer (2-FF per bit) verilogsimsyn

  A 4-bit bus synchronizer using a two-stage flip-flop per bit to safely transfer asynchronous signals into a synchronous domain.

• 4-Bit Gray Bus Synchronizer verilogsimsyn

  A 3-stage synchronizer for crossing a 4-bit Gray code bus between asynchronous clock domains.

• Async Handshake Pulse Bridge verilogsimsyn

  Crosses a single-cycle pulse from src_clk to dst_clk using a req/ack toggle handshake.

• Asynchronous Reset Synchronizer for FIFO Gray Pointer Crossings systemverilogsimsyn

  2-stage asynchronous reset synchronizer chain for safe Gray-coded FIFO pointer synchronization across clock domains with active-low reset handling.

• Enable Level Synchronizer verilogsimsyn

  Synchronizes a level enable signal from src_clk to dst_clk using a 2-FF chain.

• Handshake CDC with 8-Bit Payload verilogsimsyn

  Reliable asynchronous clock domain crossing using a two-way handshake protocol for 8-bit data payloads.

• Multi-Bit Bus Synchronizer (2-FF) verilogsimsyn

  Synchronizes an 8-bit bus using a two-flop synchronizer chain per bit — educational follow-on to single-bit two_ff_sync.

• Multi-Bit Mux-Select Synchronizer verilogsimsyn

  Synchronizes a 2-bit select signal across clock domains using a two-stage synchronizer chain.

• Req/Ack Payload Hold 8-bit verilogsimsyn

  Asynchronous clock domain crossing module for 8-bit payloads using Req/Ack handshake with backpressure.

• Single-Cycle Pulse Synchronizer (2-FF + Edge Detector) systemverilogsimsyn

  Transfers a single-clock-cycle pulse across asynchronous clock domains using a 2-FF synchronizer, edge detector, and pulse stretcher. Supports clock ratios up to 10:1 and variable reset polarity.

• Slow-Enable Fast Sample-Hold verilogsimsyn

  Samples data on a rising edge of a synchronized slow enable signal in a fast clock domain.

• Toggle Synchronizer 1-Bit verilogsimsyn

  Toggle Synchronizer 1-Bit

• Two-Flip-Flop Synchronizer Chain systemverilogsimsyn

  A two-stage flip-flop synchronizer for safe crossing of asynchronous single-bit signals into a synchronous clock domain, supporting configurable reset type and clock enable.

• Two-Stage Synchronizer Chain verilogsimsyn

  Parameterized two-stage synchronizer for single-bit asynchronous signal crossing with optional async reset support.

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