Edge, Debounce & Pulse

IP blocks

• 2-Bit Edge Detector with Edge Type Selection verilogsimsyn

  A synchronous 2-bit edge detector that emits one-cycle rise, fall, and transition pulses per bit on din changes.

• 8-Bit Sticky OR Accumulator verilogsimsyn

  An 8-bit synchronous sticky OR accumulator with active-low reset and active-high clear.

• Both-Edge Detector verilogsimsyn

  Detects both rising and falling edges of a single-bit input signal and generates a one-cycle pulse.

• Configurable Minimum Pulse Stretcher verilogsimsyn

  Ensures output pulse width is at least min_width cycles using synchronous reset and single clock domain.

• Double-Pulse Rejector verilogsimsyn

  Passes first pulse, rejects subsequent pulses within N cycles.

• Edge Count Window 8-bit verilogsimsyn

  Counts rising edges on a single-bit input signal within a configurable time window.

• Edge-Triggered Single-Cycle Pulse Generator verilogsimsyn

  Generates a 1-cycle-wide pulse on rising edge detection of input signal; latch-free, synchronous reset, single-clock-domain.

• Falling-Edge Hold for N Cycles verilogsimsyn

  Generates a configurable N-cycle pulse on output when a falling edge is detected on input.

• Level-Change Sticky Flag verilogsimsyn

  Detects rising or falling edges on a single-bit input and latches the event until acknowledged.

• Level-to-Pulse Enable verilogsimsyn

  Converts a synchronous level signal into a single-cycle pulse on rising edge detection.

• Min-Width Pulse Filter N verilogsimsyn

  Filters input pulses to ensure they meet a minimum width of N clock cycles.

• Pulse Gap Detector 8-bit verilogsimsyn

  Detects if the time interval between consecutive input pulses exceeds a configurable 8-bit threshold.

• Pulse Width Monitor verilogsimsyn

  Measures the width of an input pulse in clock cycles and latches the result.

• Quadrature Decoder x4 verilogsimsyn

  A quadrature decoder IP supporting four independent channels with x4 decoding resolution and accumulated count output.

• Rising-Edge Event Counter 8-Bit verilogsimsyn

  An 8-bit counter that increments on rising edges of an input signal with enable and clear controls.

• Rising-Edge Hold for N Cycles verilogsimsyn

  Detects rising edges and holds output high for N clock cycles, supporting pulse stretching.

• Single-Cycle Pulse Generator with Enable Gating verilogsimsyn

  Generates a single-clock-cycle-wide high pulse on rising edge of req, gated by enable signal. Fully synchronous, resettable, and synthesizable.

• Synchronized Debouncer with Edge Detection verilogsimsyn

  A synchronized debouncer that filters noisy input signals and provides clean edge detection pulses.

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