Logic Gates

IP blocks

• 2-Input AND Gate verilogsimsyn

  A basic 2-input AND gate implemented in Verilog.

• 2-Input NAND Gate verilogsimsyn

  A basic 2-input NAND gate implemented in Verilog.

• 2-Input NOR Gate verilogsimsyn

  A simple 2-input NOR gate module for combinational logic.

• 2-Input OR Gate verilogsimsyn

  A basic 2-input OR gate implemented in Verilog for digital logic design.

• 2-Input XOR Gate verilogsimsyn

  Basic 2-input XOR logic gate implementation in Verilog.

• 3-Input Bitwise NOR Gate verilogsimsyn

  A configurable-width combinational module that performs a bitwise NOR operation on three input vectors.

• 3-Input Majority Voter verilogsimsyn

  Combinational logic module that outputs the majority value of three binary inputs.

• 3-State Buffer with Enable and High-Z verilogsimsyn

  A synchronous 3-state buffer with enable control and active-low reset, outputting High-Z when disabled.

• 5-Input Majority Voter with Fault Tolerance verilogsimsyn

  Combinational 5-input majority voter with a tie flag for boundary cases.

• 8-Bit Bitwise XNOR Gate verilogsimsyn

  An 8-bit combinational logic gate that performs bitwise XNOR operations on two input vectors.

• 8-Bit NAND Reduction verilogsimsyn

  Computes the NAND of all bits in an 8-bit input vector.

• 8-Input Majority Voter verilogsimsyn

  Combinational logic that outputs high when 5 or more of 8 inputs are high.

• Bitwise Mask AND/OR 8-bit verilogsimsyn

  An 8-bit combinational logic module that performs bitwise AND or OR operations based on a mode select signal.

• OR-Reduce 8-Bit verilogsimsyn

  Combinational 8-bit OR-reduce gate producing a single output bit.

• Priority Mask-Below 8-bit verilogsimsyn

  Generates a mask of all bits strictly below the highest set bit in an 8-bit request vector.

• XOR-Reduce Tree 8-bit verilogsimsyn

  An 8-bit XOR-reduce tree that computes the parity of an 8-bit input vector using a hierarchical binary tree structure.

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