Part 0 · Warming Up 1
0.1
HELLO RTLSTUDIO
Verilog Class | 0.1 Hello RtlStudio | RTLStudio RTLStudio · Ready to play · Introduce RtlStudio simulation via $display and a wire-through DUT. 2
0.2
MY FIRST RTL
Verilog Class | 0.2 My First RTL | RTLStudio RTLStudio · Ready to play · Write and verify a 2-input AND gate in Verilog using assign and &. Part 1 · Verilog Core Syntax Data Types 3
1.1
WIRE VS REG
Verilog Class | 1.1 wire vs reg | RTLStudio RTLStudio · Ready to play 4
1.2
UNDERSTANDING BUSES
Coming soon
Verilog Class | 1.2 Understanding Buses | RTLStudio RTLStudio · Coming soon · daily upload · Declare multi-bit buses and assign hexadecimal literals in Verilog.
Combinational Logic 5
2.1
BASIC OPERATORS
Coming soon
Verilog Class | 2.1 Basic operators | RTLStudio RTLStudio · Coming soon · daily upload
6
2.2
CONCATENATION
Coming soon
Verilog Class | 2.2 Concatenation | RTLStudio RTLStudio · Coming soon · daily upload · Bundle signals with the concatenation operator to build wider buses.
Sequential Logic 7
3.1
IF ELSE AND
Coming soon
Verilog Class | 3.1 if-else and case | RTLStudio RTLStudio · Coming soon · daily upload
8
3.2
BLOCKING VS NON
Coming soon
Verilog Class | 3.2 Blocking vs non-blocking | RTLStudio RTLStudio · Coming soon · daily upload
Hierarchy & Advanced 9
4.1
INSTANTIATION
Coming soon
Verilog Class | 4.1 Instantiation | RTLStudio RTLStudio · Coming soon · daily upload
10
4.2
PARAMETER VS LOCALPARA
Coming soon
Verilog Class | 4.2 parameter vs localparam | RTLStudio RTLStudio · Coming soon · daily upload
11
4.3
GENERATE STATEMENT
Coming soon
Verilog Class | 4.3 generate statement | RTLStudio RTLStudio · Coming soon · daily upload
12
4.4
FUNCTION VS TASK
Coming soon
Verilog Class | 4.4 function vs task | RTLStudio RTLStudio · Coming soon · daily upload
13
4.5
SYSTEM TASKS
Coming soon
Verilog Class | 4.5 System tasks | RTLStudio RTLStudio · Coming soon · daily upload
14
4.6
VERILOG HEADERS
Coming soon
Verilog Class | 4.6 Verilog headers | RTLStudio RTLStudio · Coming soon · daily upload
Part 2 · Practical Hardware Design Testbench & Base Logic 15
5.1
DELAY CONTROL
Coming soon
Verilog Class | 5.1 Delay control | RTLStudio RTLStudio · Coming soon · daily upload
16
5.2
CLOCK AND RESET
Coming soon
Verilog Class | 5.2 Clock and reset | RTLStudio RTLStudio · Coming soon · daily upload
17
5.3
D FLIP FLOP
Coming soon
Verilog Class | 5.3 D Flip-Flop | RTLStudio RTLStudio · Coming soon · daily upload
Data Handling 18
6.1
OVERFLOW
Coming soon
Verilog Class | 6.1 Overflow | RTLStudio RTLStudio · Coming soon · daily upload
19
6.2
SIGNED VS UNSIGNED
Coming soon
Verilog Class | 6.2 Signed vs unsigned | RTLStudio RTLStudio · Coming soon · daily upload
Counter 20
7.1
BASIC COUNTER
Coming soon
Verilog Class | 7.1 Basic counter | RTLStudio RTLStudio · Coming soon · daily upload
21
7.2
ROLLOVER AND ENABLE
Coming soon
Verilog Class | 7.2 Rollover and enable | RTLStudio RTLStudio · Coming soon · daily upload
Pipeline 22
8.1
PIPELINE CONCEPT
Coming soon
Verilog Class | 8.1 Pipeline concept | RTLStudio RTLStudio · Coming soon · daily upload
23
8.2
PIPELINE VS NON
Coming soon
Verilog Class | 8.2 Pipeline vs non-pipeline | RTLStudio RTLStudio · Coming soon · daily upload
24
8.3
DATA VALID SYNC
Coming soon
Verilog Class | 8.3 Data Valid sync | RTLStudio RTLStudio · Coming soon · daily upload
FSM (Finite State Machine) 25
9.1
3 ALWAYS BLOCK
Coming soon
Verilog Class | 9.1 3-always-block FSM | RTLStudio RTLStudio · Coming soon · daily upload · Implement the state register update in a three-always-block FSM.
26
9.2
VENDING MACHINE BASIC
Coming soon
Verilog Class | 9.2 Vending machine basic | RTLStudio RTLStudio · Coming soon · daily upload
27
9.3
VENDING MACHINE ADVANC
Coming soon
Verilog Class | 9.3 Vending machine advanced | RTLStudio RTLStudio · Coming soon · daily upload
Memory Interface 28
10.1
MEMORY INTERFACE BASIC
Coming soon
Verilog Class | 10.1 Memory interface basics | RTLStudio RTLStudio · Coming soon · daily upload
29
10.2
BRAM TIMING
Coming soon
Verilog Class | 10.2 BRAM timing | RTLStudio RTLStudio · Coming soon · daily upload
Part 3 · Next Frontier The Bridge to SV 30
11.1
LOGIC AND SV
Coming soon
Verilog Class | 11.1 logic and .sv | RTLStudio RTLStudio · Coming soon · daily upload
RTL Studio
Open IDE