Part 0 · SoC Warming Up
What is a mini-SoC?
1 0.1 WHAT IS A Coming soon SoC Class | 0.1 What is a mini-SoC? | RTLStudioRTLStudio·Coming soon · daily upload
Explore SoC Hierarchy
2 0.2 EXPLORE A PRE Coming soon SoC Class | 0.2 Explore a pre-built SoC tree | RTLStudioRTLStudio·Coming soon · daily upload
Part 1 · Address Map & Decode
Memory Map Table
3 1.1 MEMORY MAP TABLE Coming soon SoC Class | 1.1 Memory map table design | RTLStudioRTLStudio·Coming soon · daily upload
Address Hit
4 1.2 COMBINATIONAL ADDRESS Coming soon SoC Class | 1.2 Combinational address hit | RTLStudioRTLStudio·Coming soon · daily upload
One-Hot Slave Select
5 1.3 ONE HOT SLAVE Coming soon SoC Class | 1.3 One-hot slave select | RTLStudioRTLStudio·Coming soon · daily upload
AXI-Lite Decode Wrapper
6 1.4 AXI LITE DECODE Coming soon SoC Class | 1.4 AXI-Lite decode wrapper | RTLStudioRTLStudio·Coming soon · daily upload
RW Permission Gates
7 1.5 READ WRITE PERMISSION Coming soon SoC Class | 1.5 Read/write permission gates | RTLStudioRTLStudio·Coming soon · daily upload
Multi-Slave Interconnect
8 1.6 MULTI SLAVE INTERCONNE Coming soon SoC Class | 1.6 Multi-slave interconnect lite | RTLStudioRTLStudio·Coming soon · daily upload
Part 2 · Peripheral Islands
GPIO CSR Block
9 2.1 GPIO REGISTER BLOCK Coming soon SoC Class | 2.1 GPIO register block | RTLStudioRTLStudio·Coming soon · daily upload
Timer Tick
10 2.2 TIMER TICK GENERATOR Coming soon SoC Class | 2.2 Timer / tick generator | RTLStudioRTLStudio·Coming soon · daily upload
UART CSR Hook
11 2.3 UART CSR HOOK Coming soon SoC Class | 2.3 UART CSR hook (lite) | RTLStudioRTLStudio·Coming soon · daily upload
IRQ Status Enable Clear
12 2.4 IRQ STATUS ENABLE Coming soon SoC Class | 2.4 IRQ status / enable / clear | RTLStudioRTLStudio·Coming soon · daily upload
IRQ Aggregator
13 2.5 IRQ AGGREGATOR OR Coming soon SoC Class | 2.5 IRQ aggregator (OR tree) | RTLStudioRTLStudio·Coming soon · daily upload
Peripheral Subsystem Top
14 2.6 PERIPHERAL SUBSYSTEM T Coming soon SoC Class | 2.6 Peripheral subsystem top | RTLStudioRTLStudio·Coming soon · daily upload
Part 3 · System Control
Reset Sequencing
15 3.1 RESET SEQUENCING Coming soon SoC Class | 3.1 Reset sequencing | RTLStudioRTLStudio·Coming soon · daily upload
Clock Enables
16 3.2 CLOCK ENABLES GATING Coming soon SoC Class | 3.2 Clock enables & gating intro | RTLStudioRTLStudio·Coming soon · daily upload
Boot Reset Vector
17 3.3 BOOT RESET VECTOR Coming soon SoC Class | 3.3 Boot / reset vector CSR | RTLStudioRTLStudio·Coming soon · daily upload
System ID Version
18 3.4 SYSTEM ID VERSION Coming soon SoC Class | 3.4 System ID / version regs | RTLStudioRTLStudio·Coming soon · daily upload · Expose read-only chip ID and revision CSRs in the SoC IP.
Watchdog Tie-In
19 3.5 WATCHDOG TIE IN Coming soon SoC Class | 3.5 Watchdog tie-in | RTLStudioRTLStudio·Coming soon · daily upload · Implement watchdog kick CSR and timeout IRQ logic in the SOC IP module.
Sysctrl Top
20 3.6 SYSTEM CONTROL BLOCK Coming soon SoC Class | 3.6 System control block top | RTLStudioRTLStudio·Coming soon · daily upload
Part 4 · Data Movement
AXIS Register Slice
21 4.1 AXI STREAM REGISTER Coming soon SoC Class | 4.1 AXI-Stream register slice | RTLStudioRTLStudio·Coming soon · daily upload
Mem Stream FIFO Bridge
22 4.2 MEM STREAM FIFO Coming soon SoC Class | 4.2 Mem ↔ stream FIFO bridge | RTLStudioRTLStudio·Coming soon · daily upload
DMA Descriptor CSR
23 4.3 DMA DESCRIPTOR CSR Coming soon SoC Class | 4.3 DMA descriptor CSR | RTLStudioRTLStudio·Coming soon · daily upload
Mem-to-Periph DMA
24 4.4 MEMORY TO PERIPHERAL Coming soon SoC Class | 4.4 Memory-to-peripheral DMA | RTLStudioRTLStudio·Coming soon · daily upload
Periph-to-Mem DMA
25 4.5 PERIPHERAL TO MEMORY Coming soon SoC Class | 4.5 Peripheral-to-memory DMA | RTLStudioRTLStudio·Coming soon · daily upload
DMA Engine Top
26 4.6 DMA ENGINE TOP Coming soon SoC Class | 4.6 DMA engine top | RTLStudioRTLStudio·Coming soon · daily upload · Integrate descriptor CSR and transfer FSMs in dma_engine_top.
Part 5 · Integration & Capstone
CPU Stub Master
27 5.1 FIXED MASTER CPU Coming soon SoC Class | 5.1 Fixed master CPU stub | RTLStudioRTLStudio·Coming soon · daily upload
Connect Decode and Periph
28 5.2 CONNECT DECODE PERIPHE Coming soon SoC Class | 5.2 Connect decode + peripherals | RTLStudioRTLStudio·Coming soon · daily upload
Attach DMA and IRQ
29 5.3 ATTACH DMA IRQ Coming soon SoC Class | 5.3 Attach DMA + IRQ to fabric | RTLStudioRTLStudio·Coming soon · daily upload
System-Level Testbench
30 5.4 SYSTEM LEVEL TESTBENCH Coming soon SoC Class | 5.4 System-level testbench | RTLStudioRTLStudio·Coming soon · daily upload
Mini-SoC Capstone
31 5.5 ULTIMATE MINI SOC Coming soon SoC Class | 5.5 Ultimate mini-SoC | RTLStudioRTLStudio·Coming soon · daily upload