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Lectures

Four masterclass tracks (30 lessons each). Expand a course for the full public outline. Open the IDE Lecture panel to run each lesson — zip bodies and RTL are not mirrored on this page.

• Verilog Masterclass

  Free

  30 lessons · 4 parts

  Write Verilog RTL in the browser, run simulation, read VCD waveforms, and review Yosys synthesis — no desktop EDA install.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · Warming Up

  Get comfortable with RtlStudio before diving into syntax.

  1. 0.1 · Hello RtlStudio — Introduce RtlStudio simulation via $display and a wire-through DUT.
  2. 0.2 · My First RTL — Write and verify a 2-input AND gate in Verilog using assign and &.

  Part 1 · Verilog Core Syntax

  Language mechanics first — confirm behavior on waveforms, not big designs yet.

  1. 1.1 · wire vs reg — Declare ports as wire or reg based on assignment style in combinational vs sequential logic.
  2. 1.2 · Understanding Buses — Declare multi-bit buses and assign hexadecimal literals in Verilog.
  3. 2.1 · Basic operators — Basic Verilog operators (+, &, |) using continuous assignments in combinational logic.
  4. 2.2 · Concatenation — Bundle signals with the concatenation operator to build wider buses.
  5. 3.1 · if-else and case — Implement a 4-to-1 multiplexer using case statements and verify all select branches.
  6. 3.2 · Blocking vs non-blocking — Use non-blocking assignments in clocked always blocks to model flip-flops correctly.
  7. 4.1 · Instantiation — Instantiate sub-modules using named port mapping and connect them in a testbench.
  8. 4.2 · parameter vs localparam — Use parameter (externally overridable) vs localparam (fixed internal constant) in modules.
  9. 4.3 · generate statement — Use generate-for loops to automate hardware instantiation for scalable RTL.
  10. 4.4 · function vs task — When to use functions (combinational, no timing) vs tasks (simulation timing, delays).
  11. 4.5 · System tasks — Use $readmemb to initialize memory arrays from text files in testbenches.
  12. 4.6 · Verilog headers — Verilog header files (.vh) with ` include ` and define `` macros for global constants.

  Part 2 · Practical Hardware Design

  Apply syntax to the blocks non-memory RTL engineers build in practice.

  1. 5.1 · Delay control — Use delay controls (#N) in testbenches to sequence stimulus at precise simulation times.
  2. 5.2 · Clock and reset — Generate a continuous clock and properly deassert asynchronous reset to initialize a clocked register.
  3. 5.3 · D Flip-Flop — Complete the sensitivity list for a D flip-flop with asynchronous reset to prevent latch inference.
  4. 6.1 · Overflow — Detect overflow in an N-bit counter by comparing count to its maximum value.
  5. 6.2 · Signed vs unsigned — Use $signed() casting for correct signed arithmetic and avoid misinterpretation of bit patterns.
  6. 7.1 · Basic counter — Build and verify an 8-bit synchronous up-counter with a minimal testbench.
  7. 7.2 · Rollover and enable — Implement a counter that increments only when enabled and resets at a custom maximum value.
  8. 8.1 · Pipeline concept — Implement a 2-stage pipeline to compute (A + B) * C across register stages.
  9. 8.2 · Pipeline vs non-pipeline — Compare latency and throughput of pipelined vs non-pipelined multiplier implementations.
  10. 8.3 · Data Valid sync — Synchronize the valid control signal through a multi-stage pipeline alongside data.
  11. 9.1 · 3-always-block FSM — Implement the state register update in a three-always-block FSM.
  12. 9.2 · Vending machine basic — Implement next-state logic for a 4-state vending machine FSM from coin inputs.
  13. 9.3 · Vending machine advanced — Implement output logic for a vending machine FSM to drive dispense and change in the COIN3 state.
  14. 10.1 · Memory interface basics — Implement synchronous memory write logic and verify read-after-write for a 16×8-bit array.
  15. 10.2 · BRAM timing — Synchronous BRAM 1-cycle read latency; register the read address in the DUT.

  Part 3 · Next Frontier

  1. 11.1 · logic and .sv — Transition from Verilog to SystemVerilog by replacing wire/reg with unified logic in a memory-based DUT.
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• SystemVerilog Masterclass

  Pro

  30 lessons · 4 parts

  Pro track for modern SystemVerilog design and verification — logic, interfaces, packages, OOP, constrained-random, coverage, SVA, and Mini-UVM.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · SV Warming Up

  Move from Verilog to SystemVerilog and get the Verilator simulation flow running.

  1. 0.1 · logic and design.sv — Introduce the unified logic type in SystemVerilog to replace legacy wire/reg in simple combinational logic.
  2. 0.2 · Goodbye wire/reg, Hello logic — Replace legacy wire/reg with logic in module ports and internal signals to unify net/variable semantics.

  Part 1 · Design in SV

  Synthesizable SystemVerilog that removes Verilog ambiguity and cuts boilerplate.

  1. 1.1 · typedef and enum — Declare and use typedef enums for FSM state names instead of raw integers.
  2. 1.2 · Packed vs Unpacked arrays — See how packed and unpacked arrays differ in syntax, memory layout, and slicing behavior.
  3. 1.3 · struct (Structures) — Define packed structs to group control and payload fields into a single packet type.
  4. 1.4 · string and $sformatf — Use string variables and $sformatf for formatted simulation logging in testbenches.
  5. 1.5 · always_comb — Use always_comb blocks for safe, explicit combinational logic — no sensitivity list required.
  6. 1.6 · always_ff — Model clocked sequential registers with always_ff, asynchronous reset, and non-blocking assignments.
  7. 1.7 · interface basics — Bundle shared signals into an interface to simplify DUT wiring and improve modularity.
  8. 1.8 · modports — Use modports to define and enforce input/output directions for master and slave endpoints.
  9. 1.9 · package and import — Define and import packages to centralize shared types and constants across design and testbench.

  Part 2 · Verification & OOP

  Software-side verification: dynamic data structures, classes, and the first UVM master keys.

  1. 2.1 · Dynamic Arrays — Allocate dynamic arrays at runtime with new[] in testbench code.
  2. 2.2 · Queues — Use push_back() and pop_front() to manage dynamic data buffers with queues.
  3. 2.3 · Associative Arrays — Declare associative arrays with correct index types for sparse memory modeling.
  4. 2.4 · Class and Handle — Define classes and instantiate handles for object-oriented verification.
  5. 2.5 · local and static members — Use static and local members to share state and hide internal class data.
  6. 2.6 · virtual interface — Connect verification classes to hardware instances using virtual interfaces.
  7. 2.7 · Inheritance (extends) — Use extends to inherit and extend class definitions for verification reuse.
  8. 2.8 · virtual methods — Enable polymorphism with virtual methods so child classes can override behavior.

  Part 3 · Advanced SV & Mini-UVM

  Timing, concurrency, constrained-random verification, assertions, and a pure-SV Mini-UVM environment.

  1. 3.1 · Downcasting with $cast (UVM Key 2) — Safely downcast class handles with $cast for UVM-style verification.
  2. 3.2 · clocking block — Define a clocking block to synchronize stimulus with the DUT clock and avoid race conditions.
  3. 3.3 · mailbox — Pass transactions between generator and driver threads with mailbox put/get.
  4. 3.4 · semaphore — Use semaphores so parallel threads acquire shared resources without collision.
  5. 3.5 · Constraint Random (rand/randomize) — Generate unpredictable stimulus with rand and randomize() to hit corner-case bugs.
  6. 3.6 · constraint blocks — Limit random value generation to valid protocol ranges with constraint blocks.
  7. 3.7 · functional coverage (manual bins, Verilator) — Implement manual functional coverage with explicit bin comparisons in a Verilator-safe testbench.
  8. 3.8 · Immediate Assertions — Use immediate assertions in testbenches to catch bugs exactly when they happen.
  9. 3.9 · Concurrent Assertions (SVA) — Define and verify a next-cycle request–acknowledge protocol with concurrent assertions.
  10. 3.10 · Mini-UVM: Architecture (Theory) — Introduce the UVM component hierarchy through a minimal, observe-only testbench.
  11. 3.11 · Mini-UVM: Full Integration (Capstone) — Wire the virtual interface and mailbox inside the environment class to complete a Mini-UVM skeleton.
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• UVM Masterclass

  Pro

  30 lessons · 6 parts

  Pro UVM verification track — FIFO CDV missions, agents, scoreboards, factory overrides, virtual sequences, APB, and UVM RAL.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · UVM Warming Up

  How SystemVerilog classes evolve into the UVM verification framework.

  1. 0.1 · Hello UVM: macros and uvm_info — Introduce UVM logging with uvm_info in a console-first testbench without UVM components.
  2. 0.2 · Time master: UVM phase schedule — Implement build, connect, run, and report phases in a test class and observe execution order.

  Part 1 · Stimulus Generation

  Create randomized transactions and deliver them safely to the DUT.

  1. 1.1 · UVM sequence item and uvm_field macros — Define a FIFO sequence item and register fields with uvm_field macros for copy, compare, and print.
  2. 1.2 · UVM sequence and uvm_do in body() — Generate FIFO write transactions with a UVM sequence using uvm_do in body().
  3. 1.3 · Controlled randomness for FIFO traffic — Constrain sequence items to produce valid mixed read/write FIFO traffic patterns.
  4. 1.4 · UVM sequencer delivery path — Wire the sequencer to route sequence items from sequence to driver.

  Part 2 · Agent: Driver & Monitor

  Connect software UVM components to hardware FIFO pins.

  1. 2.1 · Driver: seq_item_port.get_next_item() — Retrieve the next transaction from the sequencer with get_next_item() in run_phase.
  2. 2.2 · Virtual interface via uvm_config_db — Pass a virtual interface from tb_top to the driver through uvm_config_db.
  3. 2.3 · Handshake: item_done() and wave analysis — Complete the driver handshake with item_done() and analyze timing on VCD waveforms.
  4. 2.4 · UVM monitor: sample FIFO pins — Sample FIFO interface signals on the clock edge and reconstruct transactions.
  5. 2.5 · Analysis port: broadcast monitored data — Use analysis ports to broadcast monitored transactions to downstream components.

  Part 3 · Env and Coverage

  Assemble the verification environment, compare data, and hunt coverage.

  1. 3.1 · UVM agent: active vs passive is_active — Build a reusable agent with is_active to switch between active and passive (monitor-only) modes.
  2. 3.2 · TLM analysis FIFO into the scoreboard — Connect a TLM analysis FIFO between monitor and scoreboard so samples are not lost.
  3. 3.3 · UVM scoreboard compare() and uvm_error — Compare expected and actual FIFO transactions and raise uvm_error on mismatch.
  4. 3.4 · UVM env: verification environment pack — Wire agent and scoreboard into a reusable environment in build_phase and connect_phase.
  5. 3.5 · UVM subscriber and covergroup on analysis port — Encapsulate functional coverage in a subscriber with a FIFO full/empty covergroup on the analysis port.
  6. 3.6 · CDV: hit FIFO full and reach 100% coverage — Tune sequence constraints to flood writes until the FIFO-full coverpoint hits and LCOV reaches 100%.

  Part 4 · Advanced UVM

  Factory, config objects, virtual sequences, and pipelined drivers for large SoC verification.

  1. 4.1 · UVM test: orchestrate env and sequences — Orchestrate the environment and sequences from a top-level UVM test class.
  2. 4.2 · raise_objection / drop_objection time control — Use phase objections to keep run_phase alive until stimulus completes.
  3. 4.3 · UVM factory: type_id::create() — Allocate components with type_id::create() instead of new() for flexible substitution.
  4. 4.4 · Factory override: swap in error-injection sequence — Override the factory to replace a normal sequence with an error-injection sequence without editing base code.
  5. 4.5 · Configuration object for agent settings — Bundle agent and env settings into one config object and pass it via uvm_config_db.
  6. 4.6 · Virtual sequence: multi-agent fork-join conductor — Coordinate parallel write and read sequences on separate sequencers with a virtual sequence and fork–join.
  7. 4.7 · Pipelined driver: separate get() and put() (AXI prep) — Refactor the driver to use separate get() and put() in parallel threads for AXI-style pipelining.

  Part 5 · AMBA APB and UVM RAL

  APB protocol, register abstraction, and the roadmap to AXI.

  1. 5.1 · AMBA APB: PSEL, PENABLE, PWRITE timing — Learn APB SETUP/ACCESS timing and verify slave behavior in simulation.
  2. 5.2 · Why UVM RAL maps registers to objects — Map APB registers (CTRL/STAT/DATA) to uvm_reg objects in a register block.
  3. 5.3 · RAL adapter: reg ops to APB bus transactions — Implement a register adapter that translates register operations into APB bus transactions.
  4. 5.4 · Mission: reg_model frontdoor write() one-liner — Control APB registers with a single RAL frontdoor write() instead of raw bus sequences.
  5. 5.5 · Mission: APB register field coverage 100% — Exercise all APB register fields via UVM RAL and reach 100% field coverage with LCOV.
  6. 5.6 · Next level: AXI masterclass invitation (AXI4-Lite demo) — Contrast AXI4-Lite’s pipelined channels with APB and preview the AXI masterclass path.
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• AXI Masterclass

  Pro

  30 lessons · 6 parts

  Pro AMBA AXI4 design and UVM verification — AXI4-Lite, burst, outstanding/out-of-order, SVA checkers, and a 2×2 interconnect capstone.

  **30 lessons** · about 5 minutes each · roughly 3 hours total

  Full outline (30 lessons)

  Part 0 · AXI Foundation

  Bundle AXI’s five channels into modern SystemVerilog interfaces.

  1. 0.1 · AXI Protocol Overview: VALID/READY handshake — Introduce the AXI VALID/READY handshake and implement a simple synchronous sink in RTL.
  2. 0.2 · AXI SV interface and modport: master and slave directions — Bundle AXI signals into an SV interface and define master/slave modport directions.

  Part 1 · AXI4-Lite RTL Design

  Design an AXI4-Lite slave in pure SystemVerilog.

  1. 1.1 · Write channels (AW, W, B) RTL: AWREADY and WREADY handshake — Implement AXI4-Lite write channel handshake logic for AWREADY and WREADY.
  2. 1.2 · Read channels (AR, R) RTL: ARREADY and RVALID handshake — Implement read channel handshake for ARREADY and RVALID.
  3. 1.3 · SV struct register map: packed CTRL, STAT, and DATA — Define packed structs for CTRL, STAT, and DATA register fields and verify in a testbench.
  4. 1.4 · AXI4-Lite slave FSM: enum states and case transitions — Control AXI4-Lite transactions with an enum-based FSM and case state transitions.
  5. 1.5 · Skid buffer: decouple VALID/READY timing on an AXI channel — Add a skid buffer on the write data channel to break VALID/READY timing paths under backpressure.

  Part 2 · AXI4-Lite UVM Verification

  Verify the AXI4-Lite DUT with UVM and RAL.

  1. 2.1 · AXI sequence item: address, data, and UVM field macros — Define an AXI4-Lite sequence item with address, data, and response fields using UVM field macros.
  2. 2.2 · AXI driver: VALID/READY handshake and item_done — Implement AXI4-Lite driver handshake and item_done synchronization.
  3. 2.3 · AXI monitor and scoreboard: sample bus and compare registers — Passively sample the bus and verify register reads/writes with monitor and scoreboard.
  4. 2.4 · UVM RAL adapter for AXI: reg2bus and bus2reg — Translate register operations to AXI4-Lite bus transactions via reg2bus and bus2reg.
  5. 2.5 · Coverage-driven AXI verification: 100% READY backpressure mission — Hit 100% functional coverage on READY backpressure by constraining master-ready delays.

  Part 3 · AXI4 Full RTL Design

  Burst, outstanding, and a BRAM memory bridge.

  1. 3.1 · AXI4 burst and size: AWLEN and AWSIZE address stepping — Implement burst length and transfer size with AWLEN and AWSIZE address stepping.
  2. 3.2 · Write data channel: WSTRB and WLAST for write bursts — Manage WSTRB, a write beat counter, and WLAST to terminate write bursts.
  3. 3.3 · Read data channel: RLAST on the final read beat — Assert RLAST on the final beat of an AXI4 read burst.
  4. 3.4 · Outstanding transactions: AWID tracking FIFO — Track multiple in-flight write transactions with an AWID FIFO.
  5. 3.5 · Out-of-order and interleaving: observe-only routing theory — See how transaction IDs support out-of-order read responses and interleaved write beats.
  6. 3.6 · AXI4 slave memory controller: BRAM wrapper bridge — Map AXI4 write strobes to BRAM byte enables and verify burst write/readback.

  Part 4 · AXI4 Full UVM Verification

  Five-channel parallel UVM for AXI Full timing.

  1. 4.1 · Dynamic array payload: runtime-sized burst data in the sequence item — Allocate dynamic data/wstrb arrays in sequence items for variable-length bursts.
  2. 4.2 · Independent channel driver: fork/join_none on five AXI channels — Drive all five channels in parallel with fork/join_none to avoid deadlocks.
  3. 4.3 · ID tracking monitor: associative array for outstanding transactions — Track outstanding transactions by ID in the monitor for response correlation.
  4. 4.4 · Out-of-order scoreboard: match responses by BID and RID — Match write/read responses to address-phase transactions using BID/RID lookup.
  5. 4.5 · AXI virtual sequence: parallel read and write traffic — Fork parallel AXI read and write sequences to stress outstanding transaction handling.

  Part 5 · SVA and System Integration

  SVA protocol checkers, multi-master systems, and the capstone.

  1. 5.1 · SVA basics for AXI: stable data while VALID waits for READY — Enforce handshake stability: data and control remain stable while VALID is high and READY is low.
  2. 5.2 · SVA burst and ID checker: AWLEN versus WLAST beat count — Assert WLAST occurs when the AWLEN-defined beat count completes.
  3. 5.3 · AXI crossbar interconnect: observe-only routing theory — Introduction to address decoding and round-robin arbitration in multi-master systems.
  4. 5.4 · Multi-master arbiter RTL: round-robin grant logic — Implement round-robin arbitration for simultaneous master requests.
  5. 5.5 · AXI error handling: SLVERR and DECERR in UVM sequences — Handle SLVERR/DECERR responses in UVM sequences without fatal exits.
  6. 5.6 · AXI exclusive access: ARLOCK and EXOKAY response handling — Implement and verify exclusive access with ARLOCK and EXOKAY handling.
  7. 5.7 · The ultimate AXI system: 2x2 capstone with UVM, SVA, and 100% coverage — Tune virtual-sequence constraints and arbitration to reach 100% LCOV in a 2-master × 2-slave system.
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Open IP

Free examples

Crawlable starter READMEs (no login). More context on the marketing home page.

• Quick start — FSM counter

  Guided first run: lint, simulate, synthesize, then open VCD waveforms.

• Hello simulation

  Minimal smoke test for the in-browser SystemVerilog / Verilog sim path.

• UART transmitter

  Classic serial TX for simulation and waveform practice.

Open the IDE

Curriculum panels, Open IP, Verilator, Yosys, and the waveform viewer all live in the app at rtlstudio.dev. Free covers core tools and the Verilog lecture track; Pro unlocks remaining lectures and Open IP.