Pro catalog
Arithmetic & Math
Adders, multipliers, dividers, ALUs, and arithmetic datapaths.
Category overview
Adders, multipliers, dividers, ALUs, and arithmetic datapaths.
IP blocks
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A combinational 1-bit full adder module that computes sum and carry-out from three input bits.
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A basic 1-bit half adder module that computes sum and carry from two input bits.
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A 16-bit carry-select adder that splits addition into two 8-bit blocks to reduce propagation delay.
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A synchronous 16-bit two's complement signed adder with overflow detection logic.
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A 2-bit saturating up/down counter with synchronous enable and asynchronous reset.
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Combinational module that counts the number of leading zeros in a 32-bit input vector using a priority encoder approach.
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A fully combinational 32-bit equality comparator that asserts a high output when two input vectors are identical.
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Combinational 32-bit population count (Hamming weight). Returns the number of set bits in the input vector. Output width is 6 bits (max value 32).
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A 4-bit arithmetic unit supporting addition and subtraction with signed overflow detection using two's complement logic.
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A SystemVerilog implementation of a 4-digit Binary Coded Decimal adder with carry propagation, suitable for decimal arithmetic applications.
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Balanced binary tree adder that sums four 8-bit unsigned inputs into a 10-bit result.
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Combinational module to compute the absolute value of an 8-bit signed two's complement integer.
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An 8-bit Arithmetic Logic Unit supporting addition, subtraction, bitwise logic, and shift operations with carry-out flags.
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An 8-bit Carry-Save Adder that reduces three 8-bit operands into a sum vector and a carry vector using parallel full-adder slices.
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Combinational module that counts consecutive zero bits from the LSB of an 8-bit input using a lookup table.
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Combinational 8-bit unsigned integer comparator generating mutually exclusive eq, gt, and lt signals.
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A combinational 8-bit magnitude comparator that outputs gt, lt, and eq signals.
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Combinational module that outputs the minimum and maximum of two 8-bit unsigned inputs.
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An 8-bit synchronous one's complement adder that implements end-around carry logic for overflow handling.
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An 8-bit unsigned adder with configurable saturation and overflow detection.
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Combinational 8-bit saturating subtractor that outputs max(a-b, 0).
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An 8-bit synchronous subtractor with borrow-in and borrow-out support for unsigned and signed arithmetic.
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8-bit signed subtractor (A - B) with overflow detection using two's complement arithmetic.
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Synchronous 8x8 Multiply-Accumulate unit with 16-bit accumulator and clear support.
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Combinational module calculating the absolute difference between two unsigned 8-bit integers.
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A 4-digit Binary Coded Decimal subtractor with borrow propagation and pass-through mode.
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Combinational radix-4 Booth signed 4x4 multiplier with explicit partial-product recoding (not a single $signed multiply).
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A 4-bit carry-lookahead adder implementation using explicit generate and propagate terms to minimize carry propagation delay.
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Clamps a signed 8-bit input to a specified signed range [lo, hi].
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Parameterized combinational Kogge-Stone adder with carry-in, carry-out, and signed overflow detection.
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A fully parameterized Verilog ripple-carry adder with carry-in, carry-out, and signed overflow detection.
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Computes the rounded average of two 8-bit unsigned integers using (a + b + 1) >> 1.
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A combinational saturating multiply-accumulate unit that multiplies two 4-bit operands and adds them to an 8-bit accumulator, saturating to 0xFF on overflow.
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A 4-bit saturating multiplier that clamps overflow results to 15.
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Saturating cast from 16-bit signed to 8-bit signed integer, clamping to -128 or 127.
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Combinational signed 3-way comparator for 8-bit two's complement operands.