About RTL Studio
Browser HDL IDE · Verilog & SystemVerilog
Design Study (SGDH)
RTL Studio is developed with Design Study (SGDH) — courses, community, and free browser tools for Verilog / FPGA learners. How-tos: simulation · synthesis.
Copyright
© 2026 RtlStudio. All rights reserved. RTL Studio is proprietary software — see Terms of Service.
Overview
RtlStudio runs simulation, synthesis, lint, and waveform tools as WebAssembly inside your browser tab. Your RTL stays on your machine for compile and sim — nothing is sent to our servers unless you explicitly save to a cloud slot or share a link.
Principles
- Auto-install tool engines — open a tab, nothing to set up yourself
- Unlimited sim, synthesis, and lint runs on your CPU
- Monaco editor with HDL syntax highlighting
- Resizable workbench: explorer, panels, editor splits
Engines
- Icarus Verilog — Verilog simulation
- Verilator — SystemVerilog sim Pro
- Yosys — generic synthesis mapping
- SkyWater sky130 — technology mapping Pro
- Slang & Verible — lint
- Surfer & WaveDrom — VCD & timing diagrams
Workbench panels
- Explorer
- Multi-file workspaces, top module & testbench selection
- Simulation
- Icarus or Verilator runs, VCD output, coverage view
- Synthesis
- Yosys netlist, block / FSM / schematic viewers; sky130 cell mapping on Pro
- Lint
- Slang worker, Problems panel with jump-to-line
- Waveform editor
- Surfer VCD UI and WaveDrom authoring
- Tutorial & Lecture
- Examples and curriculum tracks — Verilog free; SV / UVM / AXI Pro · see Learn
- Open IP
- Reference RTL blocks with packaged results — Pro
Account & cloud
Optional Google sign-in for cloud workspace slots (Free: 3 · Pro: 10), lecture progress, and subscription sync.
Licenses
Vendored engines are listed in our Third-party notices. Copyleft components (source disclosure) are separated from permissive bundles.
Open the IDE
The same product overview lives in Help → About inside the app. Launch rtlstudio.dev to edit, lint, simulate, and synthesize in-tab.