Parity

IP blocks

• 4-Bit Parity OK Checker (XOR vs Type) verilogsimsyn

  Combinational checker: XOR of 4 data bits compared against parity_type; asserts parity_ok on match.

• 8-Bit Even/Odd Parity Bit Generator verilogsimsyn

  Generates the even or odd parity bit for an 8-bit data word (not a mismatch checker).

• 8-Bit Parity Error Counter with Accumulator verilogsimsyn

  An 8-bit parity error counter with a 16-bit accumulator. It supports configurable even and odd parity modes and includes synchronous enable and clear controls.

• 8-Bit Parity Generator (Muxed Even/Odd) verilogsimsyn

  Combinational even/odd parity generator using explicit even-parity XOR and mode mux.

• Even Parity over 16-Bit Bus verilogsimsyn

  Combinational even parity generator for a 16-bit data bus using XOR reduction.

• Hamming Distance 8-Bit verilogsimsyn

  Combinational module that calculates the Hamming distance (number of differing bits) between two 8-bit input vectors.

• Odd/Even Parity Select 8-bit verilogsimsyn

  An 8-bit combinatorial module that generates odd or even parity based on a control signal.

• Parity Byte Checker 8-Bit verilogsimsyn

  Combinational parity checker for 8-bit data supporting even and odd parity modes.

• Parity Invert-Select 8-bit verilogsimsyn

  8-bit even parity generator with optional output inversion.

• Parity-Protected 8-Bit Register verilogsimsyn

  An 8-bit register with integrated even parity protection and external fault injection support.

• SECDED Nibble Syndrome (toy) verilogsimsyn

  Toy SECDED syndrome generator for a 4-bit nibble with global parity check.

• Sticky Parity Error Flag 8-Bit verilogsimsyn

  A Verilog module that checks 8-bit data parity and latches an error flag until cleared.

• XOR-Reduce Parity Tree 16-bit verilogsimsyn

  Balanced XOR-reduction tree computing even parity for a 16-bit input vector.

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