RTL Studio Open IDE

Course order

Select a lesson to play · missing videos show Coming soon

  1. 1 0.1 HELLO UVM MACROS Coming soon UVM Class | 0.1 Hello UVM: macros and uvm_info | RTLStudioRTLStudio·Coming soon · daily upload
  2. 2 0.2 TIME MASTER UVM Coming soon UVM Class | 0.2 Time master: UVM phase schedule | RTLStudioRTLStudio·Coming soon · daily upload
  3. 3 1.1 UVM SEQUENCE ITEM Coming soon UVM Class | 1.1 UVM sequence item and uvm_field macros | RTLStudioRTLStudio·Coming soon · daily upload
  4. 4 1.2 UVM SEQUENCE AND Coming soon UVM Class | 1.2 UVM sequence and uvm_do in body() | RTLStudioRTLStudio·Coming soon · daily upload
  5. 5 1.3 CONTROLLED RANDOMNESS Coming soon UVM Class | 1.3 Controlled randomness for FIFO traffic | RTLStudioRTLStudio·Coming soon · daily upload
  6. 6 1.4 UVM SEQUENCER DELIVERY Coming soon UVM Class | 1.4 UVM sequencer delivery path | RTLStudioRTLStudio·Coming soon · daily upload · Wire the sequencer to route sequence items from sequence to driver.
  7. 7 2.1 DRIVER SEQ ITEM Coming soon UVM Class | 2.1 Driver: seq_item_port.get_next_item() | RTLStudioRTLStudio·Coming soon · daily upload
  8. 8 2.2 VIRTUAL INTERFACE VIA Coming soon UVM Class | 2.2 Virtual interface via uvm_config_db | RTLStudioRTLStudio·Coming soon · daily upload
  9. 9 2.3 HANDSHAKE ITEM DONE Coming soon UVM Class | 2.3 Handshake: item_done() and wave analysis | RTLStudioRTLStudio·Coming soon · daily upload
  10. 10 2.4 UVM MONITOR SAMPLE Coming soon UVM Class | 2.4 UVM monitor: sample FIFO pins | RTLStudioRTLStudio·Coming soon · daily upload
  11. 11 2.5 ANALYSIS PORT BROADCAS Coming soon UVM Class | 2.5 Analysis port: broadcast monitored data | RTLStudioRTLStudio·Coming soon · daily upload
  12. 12 3.1 UVM AGENT ACTIVE Coming soon UVM Class | 3.1 UVM agent: active vs passive is_active | RTLStudioRTLStudio·Coming soon · daily upload
  13. 13 3.2 TLM ANALYSIS FIFO Coming soon UVM Class | 3.2 TLM analysis FIFO into the scoreboard | RTLStudioRTLStudio·Coming soon · daily upload
  14. 14 3.3 UVM SCOREBOARD COMPARE Coming soon UVM Class | 3.3 UVM scoreboard compare() and uvm_error | RTLStudioRTLStudio·Coming soon · daily upload
  15. 15 3.4 UVM ENV VERIFICATION Coming soon UVM Class | 3.4 UVM env: verification environment pack | RTLStudioRTLStudio·Coming soon · daily upload
  16. 16 3.5 UVM SUBSCRIBER AND Coming soon UVM Class | 3.5 UVM subscriber and covergroup on analysis port | RTLStudioRTLStudio·Coming soon · daily upload
  17. 17 3.6 CDV HIT FIFO Coming soon UVM Class | 3.6 CDV: hit FIFO full and reach 100% coverage | RTLStudioRTLStudio·Coming soon · daily upload
  18. 18 4.1 UVM TEST ORCHESTRATE Coming soon UVM Class | 4.1 UVM test: orchestrate env and sequences | RTLStudioRTLStudio·Coming soon · daily upload
  19. 19 4.2 RAISE OBJECTION DROP Coming soon UVM Class | 4.2 raise_objection / drop_objection time control | RTLStudioRTLStudio·Coming soon · daily upload · Use phase objections to keep run_phase alive until stimulus completes.
  20. 20 4.3 UVM FACTORY TYPE Coming soon UVM Class | 4.3 UVM factory: type_id::create() | RTLStudioRTLStudio·Coming soon · daily upload
  21. 21 4.4 FACTORY OVERRIDE SWAP Coming soon UVM Class | 4.4 Factory override: swap in error-injection sequence | RTLStudioRTLStudio·Coming soon · daily upload
  22. 22 4.5 CONFIGURATION OBJECT F Coming soon UVM Class | 4.5 Configuration object for agent settings | RTLStudioRTLStudio·Coming soon · daily upload
  23. 23 4.6 VIRTUAL SEQUENCE MULTI Coming soon UVM Class | 4.6 Virtual sequence: multi-agent fork-join conductor | RTLStudioRTLStudio·Coming soon · daily upload
  24. 24 4.7 PIPELINED DRIVER SEPAR Coming soon UVM Class | 4.7 Pipelined driver: separate get() and put() (AXI prep) | RTLStudioRTLStudio·Coming soon · daily upload
  25. 25 5.1 AMBA APB PSEL Coming soon UVM Class | 5.1 AMBA APB: PSEL, PENABLE, PWRITE timing | RTLStudioRTLStudio·Coming soon · daily upload · Learn APB SETUP/ACCESS timing and verify slave behavior in simulation.
  26. 26 5.2 WHY UVM RAL Coming soon UVM Class | 5.2 Why UVM RAL maps registers to objects | RTLStudioRTLStudio·Coming soon · daily upload
  27. 27 5.3 RAL ADAPTER REG Coming soon UVM Class | 5.3 RAL adapter: reg ops to APB bus transactions | RTLStudioRTLStudio·Coming soon · daily upload
  28. 28 5.4 MISSION REG MODEL Coming soon UVM Class | 5.4 Mission: reg_model frontdoor write() one-liner | RTLStudioRTLStudio·Coming soon · daily upload
  29. 29 5.5 MISSION APB REGISTER Coming soon UVM Class | 5.5 Mission: APB register field coverage 100% | RTLStudioRTLStudio·Coming soon · daily upload
  30. 30 5.6 NEXT LEVEL AXI Coming soon UVM Class | 5.6 Next level: AXI masterclass invitation (AXI4-Lite demo) | RTLStudioRTLStudio·Coming soon · daily upload