Memory & FIFOs

IP blocks

• 16-Word 16-Bit Sync RAM with Byte Enable verilogsimsyn

  A synchronous RAM module with 16 words of 16-bit width, featuring byte-level write enable signals for granular data updates.

• 16×8 Sync RAM (No Reset, Registered Read) verilogsimsyn

  Sixteen-word 8-bit single-port RAM with no reset and registered (synchronous) read data out.

• 32-Bit Asynchronous FIFO with Gray Pointer Encoding systemverilogsimsyn

  A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.

• 32x16 Synchronous Single-Port RAM verilogsimsyn

  32-word by 16-bit synchronous single-port RAM with combinational read.

• 4×8 Sync RAM (Async Reset, Comb Read) verilogsimsyn

  Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.

• 64-bit Wide Scratchpad RAM with Dual-Port Access verilogsimsyn

  256x64 dual-port RAM with byte-enable masking and combinational reads.

• 8-Bit Valid/Ready Skid Buffer verilogsimsyn

  An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.

• 8x16 Single-Port Sync RAM verilogsimsyn

  8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).

• 8x32 Dual-Read Register File verilogsimsyn

  An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.

• 8×8 Sync RAM (Async Reset, Comb Read, Loop Init) verilogsimsyn

  Eight-word 8-bit single-port RAM with async reset via loop init, synchronous write, and combinational read.

• Asymmetric RAM WR8 RD16 verilogsimsyn

  A synchronous RAM module with 8-bit write width and 16-bit read width, featuring zero-padded reads.

• Circular Buffer 16x8 verilogsimsyn

  A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.

• Count-Based Sync FIFO with Dual Ready/Valid systemverilogsimsyn

  Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.

• Dual-Port RAM Write-First Bypass verilogsimsyn

  Dual-Port RAM with Write-First Bypass behavior where read data reflects write data immediately if addresses match.

• Dual-Port Register File 4x16 verilogsimsyn

  A 4x16 dual-port register file with two asynchronous read ports and one synchronous write port.

• FWFT Sync FIFO 16x8 verilogsimsyn

  First-Word-Fall-Through Synchronous FIFO with 16-word depth and 8-bit data width.

• LIFO Stack 8-Bit verilogsimsyn

  Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.

• Ping-Pong Buffer 8x8 verilogsimsyn

  An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.

• Pointer-Based Sync FIFO with Flush verilogsimsyn

  Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.

• Regfile 1W2R 8x16 verilogsimsyn

  8-word by 16-bit register file with 1 write port and 2 read ports, featuring synchronous RAW bypass.

• ROM 16x8 Case Lookup verilogsimsyn

  A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.

• Simple CAM 4-Entry x 8-Bit verilogsimsyn

  A simple Content Addressable Memory with 4 entries and 8-bit width, supporting parallel search and indexed write.

• Synchronous 64-Bit FIFO with Full/Empty Flags systemverilogsimsyn

  A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.

• Synchronous FIFO Depth Calculator (Counter-Based) verilogsimsyn

  A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.

• True Dual-Port RAM 8x8 verilogsimsyn

  True Dual-Port RAM with 8 words of 8-bit width and Port A write priority.

• Write-Priority Regfile 4x8 verilogsimsyn

  A 4x8 register file with two write ports where Port A has priority over Port B on address collision.

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