Part 0 · AXI Foundation
AXI Protocol Overview
1 0.1 AXI PROTOCOL OVERVIEW Coming soon AXI Class | 0.1 AXI Protocol Overview: VALID/READY handshake | RTLStudioRTLStudio·Coming soon · daily upload
AXI SV Interface and Modport
2 0.2 AXI SV INTERFACE Coming soon AXI Class | 0.2 AXI SV interface and modport: master and slave directions | RTLStudioRTLStudio·Coming soon · daily upload
Part 1 · AXI4-Lite RTL Design
Write Channels RTL
3 1.1 WRITE CHANNELS AW Coming soon AXI Class | 1.1 Write channels (AW, W, B) RTL: AWREADY and WREADY handshake | RTLStudioRTLStudio·Coming soon · daily upload
Read Channels RTL
4 1.2 READ CHANNELS AR Coming soon AXI Class | 1.2 Read channels (AR, R) RTL: ARREADY and RVALID handshake | RTLStudioRTLStudio·Coming soon · daily upload · Implement read channel handshake for ARREADY and RVALID.
SV Struct Register Map
5 1.3 SV STRUCT REGISTER Coming soon AXI Class | 1.3 SV struct register map: packed CTRL, STAT, and DATA | RTLStudioRTLStudio·Coming soon · daily upload
AXI4-Lite Slave FSM
6 1.4 AXI4 LITE SLAVE Coming soon AXI Class | 1.4 AXI4-Lite slave FSM: enum states and case transitions | RTLStudioRTLStudio·Coming soon · daily upload
Skid Buffer
7 1.5 SKID BUFFER DECOUPLE Coming soon AXI Class | 1.5 Skid buffer: decouple VALID/READY timing on an AXI channel | RTLStudioRTLStudio·Coming soon · daily upload
Part 2 · AXI4-Lite UVM Verification
AXI Sequence Item
8 2.1 AXI SEQUENCE ITEM Coming soon AXI Class | 2.1 AXI sequence item: address, data, and UVM field macros | RTLStudioRTLStudio·Coming soon · daily upload
AXI Driver
9 2.2 AXI DRIVER VALID Coming soon AXI Class | 2.2 AXI driver: VALID/READY handshake and item_done | RTLStudioRTLStudio·Coming soon · daily upload · Implement AXI4-Lite driver handshake and item_done synchronization.
AXI Monitor and Scoreboard
10 2.3 AXI MONITOR AND Coming soon AXI Class | 2.3 AXI monitor and scoreboard: sample bus and compare registers | RTLStudioRTLStudio·Coming soon · daily upload
UVM RAL Adapter for AXI
11 2.4 UVM RAL ADAPTER Coming soon AXI Class | 2.4 UVM RAL adapter for AXI: reg2bus and bus2reg | RTLStudioRTLStudio·Coming soon · daily upload
Coverage-Driven AXI Verification
12 2.5 COVERAGE DRIVEN AXI Coming soon AXI Class | 2.5 Coverage-driven AXI verification: 100% READY backpressure mission | RTLStudioRTLStudio·Coming soon · daily upload
Part 3 · AXI4 Full RTL Design
AXI4 Burst and Size
13 3.1 AXI4 BURST AND Coming soon AXI Class | 3.1 AXI4 burst and size: AWLEN and AWSIZE address stepping | RTLStudioRTLStudio·Coming soon · daily upload
Write Data Channel
14 3.2 WRITE DATA CHANNEL Coming soon AXI Class | 3.2 Write data channel: WSTRB and WLAST for write bursts | RTLStudioRTLStudio·Coming soon · daily upload
Read Data Channel
15 3.3 READ DATA CHANNEL Coming soon AXI Class | 3.3 Read data channel: RLAST on the final read beat | RTLStudioRTLStudio·Coming soon · daily upload · Assert RLAST on the final beat of an AXI4 read burst.
Outstanding Transactions
16 3.4 OUTSTANDING TRANSACTIO Coming soon AXI Class | 3.4 Outstanding transactions: AWID tracking FIFO | RTLStudioRTLStudio·Coming soon · daily upload · Track multiple in-flight write transactions with an AWID FIFO.
Out-of-Order and Interleaving
17 3.5 OUT OF ORDER Coming soon AXI Class | 3.5 Out-of-order and interleaving: observe-only routing theory | RTLStudioRTLStudio·Coming soon · daily upload
AXI4 Slave Memory Controller
18 3.6 AXI4 SLAVE MEMORY Coming soon AXI Class | 3.6 AXI4 slave memory controller: BRAM wrapper bridge | RTLStudioRTLStudio·Coming soon · daily upload
Part 4 · AXI4 Full UVM Verification
Dynamic Array Payload
19 4.1 DYNAMIC ARRAY PAYLOAD Coming soon AXI Class | 4.1 Dynamic array payload: runtime-sized burst data in the sequence item | RTLStudioRTLStudio·Coming soon · daily upload
Independent Channel Driver
20 4.2 INDEPENDENT CHANNEL DR Coming soon AXI Class | 4.2 Independent channel driver: fork/join_none on five AXI channels | RTLStudioRTLStudio·Coming soon · daily upload
ID Tracking Monitor
21 4.3 ID TRACKING MONITOR Coming soon AXI Class | 4.3 ID tracking monitor: associative array for outstanding transactions | RTLStudioRTLStudio·Coming soon · daily upload
Out-of-Order Scoreboard
22 4.4 OUT OF ORDER Coming soon AXI Class | 4.4 Out-of-order scoreboard: match responses by BID and RID | RTLStudioRTLStudio·Coming soon · daily upload
AXI Virtual Sequence
23 4.5 AXI VIRTUAL SEQUENCE Coming soon AXI Class | 4.5 AXI virtual sequence: parallel read and write traffic | RTLStudioRTLStudio·Coming soon · daily upload
Part 5 · SVA and System Integration
SVA Basics for AXI
24 5.1 SVA BASICS FOR Coming soon AXI Class | 5.1 SVA basics for AXI: stable data while VALID waits for READY | RTLStudioRTLStudio·Coming soon · daily upload
SVA Burst and ID Checker
25 5.2 SVA BURST AND Coming soon AXI Class | 5.2 SVA burst and ID checker: AWLEN versus WLAST beat count | RTLStudioRTLStudio·Coming soon · daily upload · Assert WLAST occurs when the AWLEN-defined beat count completes.
AXI Crossbar Interconnect
26 5.3 AXI CROSSBAR INTERCONN Coming soon AXI Class | 5.3 AXI crossbar interconnect: observe-only routing theory | RTLStudioRTLStudio·Coming soon · daily upload
Multi-Master Arbitration RTL
27 5.4 MULTI MASTER ARBITER Coming soon AXI Class | 5.4 Multi-master arbiter RTL: round-robin grant logic | RTLStudioRTLStudio·Coming soon · daily upload · Implement round-robin arbitration for simultaneous master requests.
AXI Error Handling
28 5.5 AXI ERROR HANDLING Coming soon AXI Class | 5.5 AXI error handling: SLVERR and DECERR in UVM sequences | RTLStudioRTLStudio·Coming soon · daily upload · Handle SLVERR/DECERR responses in UVM sequences without fatal exits.
AXI Exclusive Access
29 5.6 AXI EXCLUSIVE ACCESS Coming soon AXI Class | 5.6 AXI exclusive access: ARLOCK and EXOKAY response handling | RTLStudioRTLStudio·Coming soon · daily upload · Implement and verify exclusive access with ARLOCK and EXOKAY handling.
The Ultimate AXI System
30 5.7 THE ULTIMATE AXI Coming soon AXI Class | 5.7 The ultimate AXI system: 2x2 capstone with UVM, SVA, and 100% coverage | RTLStudioRTLStudio·Coming soon · daily upload