Open IP

A basic 2-input AND gate implemented in Verilog.

A basic 2-input NAND gate implemented in Verilog.

A simple 2-input NOR gate module for combinational logic.

A basic 2-input OR gate implemented in Verilog for digital logic design.

Basic 2-input XOR logic gate implementation in Verilog.

A configurable-width combinational module that performs a bitwise NOR operation on three input vectors.

Combinational logic module that outputs the majority value of three binary inputs.

A synchronous 3-state buffer with enable control and active-low reset, outputting High-Z when disabled.

Combinational 5-input majority voter with a tie flag for boundary cases.

An 8-bit combinational logic gate that performs bitwise XNOR operations on two input vectors.

Computes the NAND of all bits in an 8-bit input vector.

Combinational logic that outputs high when 5 or more of 8 inputs are high.

An 8-bit combinational logic module that performs bitwise AND or OR operations based on a mode select signal.

Combinational 8-bit OR-reduce gate producing a single output bit.

Generates a mask of all bits strictly below the highest set bit in an 8-bit request vector.

An 8-bit XOR-reduce tree that computes the parity of an 8-bit input vector using a hierarchical binary tree structure.

A 4-to-1 priority multiplexer that selects data based on a one-hot select signal, where the lowest index bit has the highest priority.

Combinational 16:1 mux with sixteen 32-bit inputs and a 4-bit select.

Latch-free combinational 32-bit 2:1 mux with no clock, reset, or enable.

Combinational 4:1 mux with four 3-bit inputs and a 2-bit select.

Combinational 4:1 mux with 8-bit inputs; active-high enable forces zero output.

Combinational 8:1 mux selecting one of eight 32-bit words when enabled.

A glitch-free 2:1 clock multiplexer that synchronizes selection signals to prevent output glitches during clock source switching.

Combinational multiplexer that selects one of 8 inputs based on a one-hot select signal, outputting zero for illegal codes.

Registered 2:1 mux with packed 2-bit din bus, active-high enable, and active-low reset.

Registered 16:1 mux with active-low enable and synchronous capture on clk.

Canonical registered 2:1 lesson IP — synchronous 8-bit mux with enable and active-low reset.

A 16-bit cycle counter with an 8-bit prescaler for configurable clock division and carry output.

Synchronous 4-digit BCD counter with up/down control, load, and carry/borrow flags.

An 8-bit binary up counter with synchronous active-low reset and enable control.

An 8-bit Johnson Counter (Twisted Ring) with synchronous reset and enable, implemented in Verilog.

An 8-bit combinational leading zero counter that outputs the count of consecutive zeros from the MSB.

An 8-bit ring counter with synchronous load and circular right shift functionality.

An 8-bit up/down counter with synchronous load and asynchronous reset.

Synchronous 4-bit bidirectional counter with enable and direction control.

A 4-bit synchronous decade BCD counter that counts 0-9 with enable control and rollover pulse generation.

An 8-bit synchronous counter with two independent compare-match outputs for event generation.

16-bit event counter with rising-edge detection and synchronous capture register.

An 8-bit Gray-code counter that converts an internal binary count to Gray code output, ensuring single-bit transitions between states.

A fully synthesizable 4-bit up counter with synchronous load, enable, and asynchronous reset capabilities.

An 8-bit loadable down counter with synchronous load, enable, and zero flag assertion. Wraps from 0 to 7 on underflow.

A parameterized modulo-N counter with asynchronous reset and terminal count output.

A synthesizable, parameterized synchronous counter with enable, asynchronous reset, and configurable wrap value.

An 8-bit counter that wraps at 0xFF and sets a sticky overflow flag upon wrapping. The flag clears only on reset or clear.

16-bit register with mutually exclusive modes: parallel load, shift left, and shift right.

Combinational 32-bit barrel with op encoding: pass-through, logical left, logical right, and rotate left.

A combinational 32-bit funnel shifter that concatenates two 32-bit inputs and shifts them left to extract a 32-bit window.

A fully synthesizable binary-tree barrel shifter supporting LSL, LSR, and ASR with clamped shift amounts and O(log N) latency.

Combinational 8-bit barrel unit controlled by mode (shift/rotate) and direction (left/right).

Combinational 8-bit bit reversal module.

Pure combinational 8-bit bit reversal module.

Combinational module that swaps the upper and lower nibbles of an 8-bit data word.

Converts 8-bit parallel input to LSB-first serial output with busy flag and synchronous load.

8-bit shift register with async reset, parallel load, serial-in, and single-direction shift enable.

Combinational 8-bit arithmetic right shift with sign extension.

Extracts an 8-bit field from a 16-bit input word using a barrel shifter and mask.

Combinational module that rotates a 32-bit word by 0 to 3 bytes.

Combinational module performing circular left shift on 8-bit data with variable shift amount.

Rotates the four 4-bit nibbles of a 16-bit word by N positions (0..3) in left or right direction.

Combinational 8-bit rotate left or right logic with configurable shift amount.

A fully synchronous 8-bit universal shift register with hold, shift left, shift right, and parallel load modes.

Combinational 16-bit priority encoder that outputs the binary index of the highest set input bit.

Converts 4-bit BCD inputs to binary with validity checking for invalid codes.

A synchronous 4-bit binary to BCD converter using the shift-and-add-3 algorithm with FSM control.

Converts a 4-bit thermometer code to a 2-bit binary value with clamping for overflow.

Encodes a 3-bit binary input into an 8-bit one-hot output.

An 8-bit priority decoder that converts a 3-bit binary index into a one-hot encoded output vector with a valid flag.

Combinational priority encoder converting 8-bit thermometer code to 3-bit binary index with MSB priority.

Combinational logic module that sign-extends an 8-bit input to a 16-bit output by replicating the MSB.

Combinational module that extends an 8-bit input to 16 bits by padding the upper 8 bits with zeros.

Converts a 4-bit binary number to its 4-bit Excess-3 equivalent.

Generate-for compare converter from 8-bit binary to a 9-bit thermometer code slice.

Case-table converter from 4-bit binary to a 15-bit thermometer code (value equals number of ones).

Registered 8-bit Gray code incrementer with Gray-to-binary and binary-to-Gray conversion logic.

Converts N-bit Gray code input to corresponding Binary output using a combinational XOR reduction chain.

Combinational priority encoder for active-low inputs, outputting one-hot encoded highest-index active request with valid flag.

Case-based one-hot decoder: 4-bit one-hot input to 2-bit binary, defaulting invalid codes to zero.

MSB-priority OR-tree decoder from 8-bit one-hot (or multi-hot) input to a 3-bit binary index.

An 8-bit thermometer code selector that outputs a one-hot code based on MSB priority.

Converts an 8-bit thermometer code to a 3-bit binary index of the highest set bit.

Combinational module that encodes the index of the least significant set bit in an 8-bit vector.

Combinational checker: XOR of 4 data bits compared against parity_type; asserts parity_ok on match.

Generates the even or odd parity bit for an 8-bit data word (not a mismatch checker).

An 8-bit parity error counter with a 16-bit accumulator. It supports configurable even and odd parity modes and includes synchronous enable and clear controls.

Combinational even/odd parity generator using explicit even-parity XOR and mode mux.

Combinational even parity generator for a 16-bit data bus using XOR reduction.

Combinational module that calculates the Hamming distance (number of differing bits) between two 8-bit input vectors.

An 8-bit combinatorial module that generates odd or even parity based on a control signal.

Combinational parity checker for 8-bit data supporting even and odd parity modes.

8-bit even parity generator with optional output inversion.

An 8-bit register with integrated even parity protection and external fault injection support.

Toy SECDED syndrome generator for a 4-bit nibble with global parity check.

A Verilog module that checks 8-bit data parity and latches an error flag until cleared.

Balanced XOR-reduction tree computing even parity for a 16-bit input vector.

A 4-channel round-robin arbiter with priority rotation to ensure fair access to shared resources.

A 4-input sliding window arbiter with configurable window size and round-robin priority.

Combinational fixed-priority arbiter for 4 request lines with static priority encoding.

Round-robin arbiter with grant hold mechanism for 4 requests.

A 4-input LRU arbiter that grants access to the requester idle the longest using a recency vector.

A lock-free arbiter that grants access to the lowest-priority active request and holds the grant until acknowledgment, supporting backpressure.

4-port Least-Recently-Granted matrix arbiter with round-robin fairness.

A 4-input token-ring arbiter that rotates a one-hot grant token to the next active requester, ensuring fair access.

A 4-requestor priority arbiter using global weight and lowest-index tie-breaking.

A synchronous 2-bit edge detector that emits one-cycle rise, fall, and transition pulses per bit on din changes.

An 8-bit synchronous sticky OR accumulator with active-low reset and active-high clear.

Detects both rising and falling edges of a single-bit input signal and generates a one-cycle pulse.

Ensures output pulse width is at least min_width cycles using synchronous reset and single clock domain.

Passes first pulse, rejects subsequent pulses within N cycles.

Counts rising edges on a single-bit input signal within a configurable time window.

Generates a 1-cycle-wide pulse on rising edge detection of input signal; latch-free, synchronous reset, single-clock-domain.

Generates a configurable N-cycle pulse on output when a falling edge is detected on input.

Detects rising or falling edges on a single-bit input and latches the event until acknowledged.

Converts a synchronous level signal into a single-cycle pulse on rising edge detection.

Filters input pulses to ensure they meet a minimum width of N clock cycles.

Detects if the time interval between consecutive input pulses exceeds a configurable 8-bit threshold.

Measures the width of an input pulse in clock cycles and latches the result.

A quadrature decoder IP supporting four independent channels with x4 decoding resolution and accumulated count output.

An 8-bit counter that increments on rising edges of an input signal with enable and clear controls.

Detects rising edges and holds output high for N clock cycles, supporting pulse stretching.

Generates a single-clock-cycle-wide high pulse on rising edge of req, gated by enable signal. Fully synchronous, resettable, and synthesizable.

A synchronized debouncer that filters noisy input signals and provides clean edge detection pulses.

A combinational 1-bit full adder module that computes sum and carry-out from three input bits.

A basic 1-bit half adder module that computes sum and carry from two input bits.

A 16-bit carry-select adder that splits addition into two 8-bit blocks to reduce propagation delay.

A synchronous 16-bit two's complement signed adder with overflow detection logic.

A 2-bit saturating up/down counter with synchronous enable and asynchronous reset.

Combinational module that counts the number of leading zeros in a 32-bit input vector using a priority encoder approach.

A fully combinational 32-bit equality comparator that asserts a high output when two input vectors are identical.

Combinational 32-bit population count (Hamming weight). Returns the number of set bits in the input vector. Output width is 6 bits (max value 32).

A 4-bit arithmetic unit supporting addition and subtraction with signed overflow detection using two's complement logic.

A SystemVerilog implementation of a 4-digit Binary Coded Decimal adder with carry propagation, suitable for decimal arithmetic applications.

Balanced binary tree adder that sums four 8-bit unsigned inputs into a 10-bit result.

Combinational module to compute the absolute value of an 8-bit signed two's complement integer.

An 8-bit Arithmetic Logic Unit supporting addition, subtraction, bitwise logic, and shift operations with carry-out flags.

An 8-bit Carry-Save Adder that reduces three 8-bit operands into a sum vector and a carry vector using parallel full-adder slices.

Combinational module that counts consecutive zero bits from the LSB of an 8-bit input using a lookup table.

Combinational 8-bit unsigned integer comparator generating mutually exclusive eq, gt, and lt signals.

A combinational 8-bit magnitude comparator that outputs gt, lt, and eq signals.

Combinational module that outputs the minimum and maximum of two 8-bit unsigned inputs.

An 8-bit synchronous one's complement adder that implements end-around carry logic for overflow handling.

An 8-bit unsigned adder with configurable saturation and overflow detection.

Combinational 8-bit saturating subtractor that outputs max(a-b, 0).

An 8-bit synchronous subtractor with borrow-in and borrow-out support for unsigned and signed arithmetic.

8-bit signed subtractor (A - B) with overflow detection using two's complement arithmetic.

Synchronous 8x8 Multiply-Accumulate unit with 16-bit accumulator and clear support.

Combinational module calculating the absolute difference between two unsigned 8-bit integers.

A 4-digit Binary Coded Decimal subtractor with borrow propagation and pass-through mode.

Combinational radix-4 Booth signed 4x4 multiplier with explicit partial-product recoding (not a single $signed multiply).

A 4-bit carry-lookahead adder implementation using explicit generate and propagate terms to minimize carry propagation delay.

Clamps a signed 8-bit input to a specified signed range [lo, hi].

Parameterized combinational Kogge-Stone adder with carry-in, carry-out, and signed overflow detection.

A fully parameterized Verilog ripple-carry adder with carry-in, carry-out, and signed overflow detection.

Computes the rounded average of two 8-bit unsigned integers using (a + b + 1) >> 1.

A combinational saturating multiply-accumulate unit that multiplies two 4-bit operands and adds them to an 8-bit accumulator, saturating to 0xFF on overflow.

A 4-bit saturating multiplier that clamps overflow results to 15.

Saturating cast from 16-bit signed to 8-bit signed integer, clamping to -128 or 127.

Combinational signed 3-way comparator for 8-bit two's complement operands.

16-bit Fibonacci LFSR with left-shift feedback and fixed max-length taps; parallel load supported.

32-bit Fibonacci LFSR with enable, parallel load, and right-shift fixed max-length taps.

64-bit LFSR with parameter TAP_SEL choosing between two fixed tap sets, plus load and enable.

8-bit Fibonacci LFSR with parallel load and right-shift feedback via mask XOR for max-length taps.

8-bit Galois LFSR with parallel load/shift enables using polynomial x^8+x^6+x^5+x^4+1.

An 8-bit parallel scrambler using an LFSR to XOR input data with a pseudo-random sequence for data whitening.

A 16-bit Additive Lagged Fibonacci pseudo-random number generator with taps j=3 and k=5.

CRC-16-CCITT Serial

Byte-serial CRC-32 generator with Ethernet-style polynomial, init 0xFFFFFFFF, and zlib-compatible output.

A SystemVerilog module that checks incoming data against a PRBS32 sequence generated by an LFSR. It counts bit errors and asserts a persistent error flag.

A 32-bit Pseudo-Random Binary Sequence generator using the IEEE 802.3 polynomial. Supports synchronous reset, enable control, and seed reload for deterministic testing.

A latch-free 32-bit pseudo-random number generator implementing the Marsaglia xorshift algorithm with synchronous seed load and asynchronous reset.

64-bit Xorshift pseudo-random number generator with seed loading and enable control.

A free-running 16-bit phase accumulator for Direct Digital Synthesis (DDS) with synchronous enable and asynchronous reset.

A simple toggle flip-flop that divides the input clock frequency by two.

A synchronous 4-phase one-hot clock-enable sequencer with enable gating and active-low reset.

Asserts clock enable for N cycles on start pulse, ignoring subsequent starts during active burst.

Generates a single-cycle clock enable pulse every N clock cycles when enabled.

A configurable clock-enable divider that generates a single-cycle pulse every N input clock cycles, gated by an input enable signal.

Stretches a 1-cycle CE pulse into N consecutive CE pulses without gating the clock.

A divide-by-3 clock generator that produces a 50% duty cycle output using a 2-bit state machine.

Captures input data on both rising and falling edges of a clock signal for DDR applications.

Synthesizable fractional clock divider using phase accumulation for low jitter.

Generates a clock enable signal with a fractional duty cycle M/N using a Bresenham accumulator.

Glitch-free clock selector using clock-enable multiplexing

Parameterized integer clock divider with 50% duty cycle supporting even divisors from 2 to 255.

Detects when a monitored clock stops toggling for N reference cycles.

Generates a periodic clock enable signal with configurable period N.

Converts an asynchronous pulse signal into a toggled clock output synchronized to a reference clock.

Combinational logic module that decodes 4-bit hexadecimal inputs into 7-segment display signals with configurable active-high or active-low polarity.

A 4b/6b Run-Length Limited encoder and decoder with disparity control for DC balance.

An 8-bit parallel differential encoder and decoder implementing NRZ-D coding with a ripple-chain XOR logic and synchronous state management.

Streaming Huffman encoder for 8-bit symbols using a precomputed static code table and ready/valid handshakes.

An 8-bit parallel-to-serial Manchester encoder with Ready/Valid handshake and backpressure support.

Combinational module that swaps the high and low nibbles of an 8-bit input word.

Combinational 8-bit parallel descrambler using a fixed XOR mask to reverse scrambling operations.

An 8-bit Run-Length Decoder that repeats an input value for a specified count.

A dual-mode 8b/10b encoder and decoder with running disparity support and control character handling.

Fully synthesizable Golay (24,12) block encoder with streaming interface and syndrome calculation.

A synchronous Hamming (7,4) error-correcting decoder that detects and corrects single-bit errors in a 7-bit codeword, outputting the corrected 4-bit data.

Hamming (7,4) Encoder

Inserts a zero bit after five consecutive one bits in a serial data stream for HDLC framing.

Removes stuffed zero bits from an HDLC serial data stream after five consecutive ones.

NRZ-to-NRZI Line Encoder

Converts NRZI encoded signals to standard NRZ format by detecting transitions.

A Reed-Solomon encoder for 8-bit symbols using GF(2^8) arithmetic with generator polynomial x^2 + 0x03*x + 0x02.

Implements 8b/10b encoding with DC balance and run-length constraints using deterministic lookup tables.

An 8-bit scrambler using a Galois LFSR with polynomial x^8 + x^6 + x^5 + x^4 + 1. It XORs input data with the LFSR state for data randomization.

A simple AHB-Lite master controller for SystemVerilog designs supporting single-cycle transactions.

Minimal AHB-Lite master that issues one read or write transfer per request.

Single-beat AHB-Lite slave with configurable address range, combinational read response, and write capture on full-word granularity.

APB3 master with setup/access phases and one outstanding transaction.

A fully compliant APB3 master controller supporting single and burst transactions with auto-increment and backpressure handling.

Configurable APB3 slave with word-aligned register file, byte-lane writes, and zero-wait-state PREADY.

A SystemVerilog IP core implementing a slave AXI-Lite interface with a 4-register bank and byte strobe support.

Single-stage AXI-Stream register slice with backpressure support and forward/reverse ready pipelining.

Single-entry skid buffer for AXI-Stream interfaces to handle backpressure.

AXI4-Lite Simple Master (Single Beat)

A basic AXI4-Lite slave module implementing a 4x32-bit register file with standard handshake protocols.

Wishbone B3 master for classic single-beat read/write transactions.

32-bit Wishbone B3 slave with combinational ack and a small register file.

Wishbone B3 slave exposing four 32-bit registers with ack on every cycle.

Converts Wishbone B3 master transactions into AHB-Lite master transactions for single-word transfers.

A Wishbone B.4 compliant slave module with byte-strobe support and a 256-byte internal memory map.

A basic Wishbone B4 Simple Master supporting single-cycle Read and Write transactions with byte masking.

A simple Wishbone slave module implementing a 4-register file with 32-bit data width and classic timing.

Single-cycle Wishbone B3 slave bridging to a configurable array of 32-bit CSRs with byte-select write support.

A robust 1-bit handshake protocol for crossing clock domains ensuring reliable data transfer without loss.

Synchronizes an asynchronous active-low reset signal to a synchronous clock domain using a 3-stage flip-flop chain to minimize metastability.

A 4-bit bus synchronizer using a two-stage flip-flop per bit to safely transfer asynchronous signals into a synchronous domain.

A 3-stage synchronizer for crossing a 4-bit Gray code bus between asynchronous clock domains.

Crosses a single-cycle pulse from src_clk to dst_clk using a req/ack toggle handshake.

2-stage asynchronous reset synchronizer chain for safe Gray-coded FIFO pointer synchronization across clock domains with active-low reset handling.

Synchronizes a level enable signal from src_clk to dst_clk using a 2-FF chain.

Reliable asynchronous clock domain crossing using a two-way handshake protocol for 8-bit data payloads.

Synchronizes an 8-bit bus using a two-flop synchronizer chain per bit — educational follow-on to single-bit two_ff_sync.

Synchronizes a 2-bit select signal across clock domains using a two-stage synchronizer chain.

Asynchronous clock domain crossing module for 8-bit payloads using Req/Ack handshake with backpressure.

Transfers a single-clock-cycle pulse across asynchronous clock domains using a 2-FF synchronizer, edge detector, and pulse stretcher. Supports clock ratios up to 10:1 and variable reset polarity.

Samples data on a rising edge of a synchronized slow enable signal in a fast clock domain.

Toggle Synchronizer 1-Bit

A two-stage flip-flop synchronizer for safe crossing of asynchronous single-bit signals into a synchronous clock domain, supporting configurable reset type and clock enable.

Parameterized two-stage synchronizer for single-bit asynchronous signal crossing with optional async reset support.

A configurable 1 MHz tick generator module with synchronous reset and single-cycle pulse output.

Reloadable 16-bit down counter that asserts match on countdown-to-zero and also when load writes zero.

A 16-bit programmable prescaler that divides the input clock frequency by (prescale + 1).

A 16-bit programmable timer module with configurable prescaler, up/down counting, and interrupt generation capabilities.

Glitch-free 16-bit PWM with shadow registers for dynamic period/duty updates, active-high output, and full verification.

A 32-bit down-counter interval timer that generates an interrupt request upon expiration, supporting preload, enable, and acknowledge signals.

A 32-bit watchdog timer with kick reload, runtime timeout reprogramming, and configurable reset pulse width.

Reloadable 8-bit down counter that pulses match_flag for one cycle when the count reaches zero.

Filters glitches on an 8-bit input bus by requiring STABLE_CYCLES consecutive unchanged samples before updating dout.

Combinational 8-bit window comparator that checks if data falls within an inclusive [lo, hi] range.

Eight-channel 16-bit PWM with global period, per-channel duty, edge/center-aligned modes, and a simplified APB-like register interface.

Sticky flag set on N-clock idle, cleared on activity pulse.

An 8-bit bang-bang thermostat controller with hysteresis for heating control.

Generates complementary drive signals with programmable dead-time to prevent shoot-through in half-bridge configurations.

Measures duty cycle from period and high-count inputs using 8-bit fixed-point arithmetic.

An 8-bit synchronous frequency counter that counts rising edges of an input signal only when a gate enable signal is active.

An 8-bit Schmitt trigger with hysteresis for noise-immune digital signal processing.

A synchronous 8-bit linear ramp generator that counts from 0 to a configurable target value.

Asserts alarm if no input pulse is detected within timeout cycles.

Generates a fixed-width output pulse in response to a trigger input, ignoring subsequent triggers during the active pulse.

A programmable one-shot timer that freezes the countdown when the 'hold' signal is asserted.

Measures the period of a periodic input signal in clock cycles using an 8-bit counter and FSM.

A retriggerable one-shot pulse generator with configurable timeout duration.

Moore Machine FSM cycling through Green, Yellow, and Red states triggered by a synchronous tick pulse.

Saturating up/down counter with fixed 8-bit limits and boundary flags.

A synchronous RAM module with 16 words of 16-bit width, featuring byte-level write enable signals for granular data updates.

Sixteen-word 8-bit single-port RAM with no reset and registered (synchronous) read data out.

A configurable 32-bit asynchronous FIFO using AXI4-Stream interfaces and Gray code pointers for safe cross-clock-domain data transfer.

32-word by 16-bit synchronous single-port RAM with combinational read.

Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.

256x64 dual-port RAM with byte-enable masking and combinational reads.

An 8-bit depth-1 skid buffer that absorbs backpressure by holding data until the consumer is ready. It asserts ready_in only when empty and maintains valid_out until valid_in deasserts.

8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).

An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.

Eight-word 8-bit single-port RAM with async reset via loop init, synchronous write, and combinational read.

A synchronous RAM module with 8-bit write width and 16-bit read width, featuring zero-padded reads.

A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.

Single-clock FIFO that tracks occupancy with an explicit count register, exposes wready/rvalid on both producer and consumer sides, and defaults to depth 64 with 16-bit data.

Dual-Port RAM with Write-First Bypass behavior where read data reflects write data immediately if addresses match.

A 4x16 dual-port register file with two asynchronous read ports and one synchronous write port.

First-Word-Fall-Through Synchronous FIFO with 16-word depth and 8-bit data width.

Synchronous LIFO stack with depth 8, 8-bit data width, full/empty flags, and overflow/underflow protection.

An 8x8 double-buffering module that swaps between two memory banks on a frame pulse for continuous data streaming.

Compact single-clock FIFO using extra-bit read/write pointers for full/empty detection, enable-style w_en/r_en ports, synchronous flush, and default depth 16 with 32-bit data.

8-word by 16-bit register file with 1 write port and 2 read ports, featuring synchronous RAW bypass.

A combinational ROM with 16 words of 8 bits, mapping 4-bit addresses to their hex values.

A simple Content Addressable Memory with 4 entries and 8-bit width, supporting parallel search and indexed write.

A synchronous FIFO module with 64-bit data width, configurable depth, and status flags for full, empty, almost full, and almost empty conditions.

A synchronous FIFO depth calculator using a counter-based approach to track buffer levels with configurable almost-full thresholds.

True Dual-Port RAM with 8 words of 8-bit width and Port A write priority.

A 4x8 register file with two write ports where Port A has priority over Port B on address collision.

Combinational 1-bit pin driver with direction control; output follows data_in or drives low in input mode.

Memory-mapped 32-bit GPIO with chip-select, DI readback of gpio_in, and byte-strobed DO register writes.

Register-mapped 8-bit GPIO with per-pin direction, data registers, and rising-edge interrupt generation.

Detects I2C bus idle conditions based on SCL and SDA levels with configurable threshold.

Detects I2C Start and Stop conditions synchronously on the SCL rising edge.

Synthesizable IEEE 1149.1 JTAG TAP Controller with 32-bit DR and IR paths.

A lightweight I²C master controller supporting Standard Mode (100 kHz) with configurable clock parameters and basic transaction control.

A lightweight I²C slave controller that translates I²C read/write operations into simple register file transfers with clock stretching support.

Minimal SPI master for CPOL=0, CPHA=0, 8-bit transfers with start/done handshake.

SPI host/controller operating in CPOL=0 CPHA=0 with 8-bit shift frames.

SPI Mode-3 Slave (CPOL=1, CPHA=1) 8-Bit

Synthesizable SPI slave with ready/valid byte interface, LSB-first Mode 0 shifting, and chip-select framed transfers.

A synthesizable 8-N-1 UART with valid/ready TX/RX handshakes and parameterizable baud timing.

8N1 UART Core with Configurable Depth TX and RX FIFOs. Supports backpressure and interrupt-ready status flags.