Pro catalog
LFSR, PRBS & CRC
LFSR, PRBS, CRC, and pseudo-random sequence generators.
Category overview
LFSR, PRBS, CRC, and pseudo-random sequence generators.
IP blocks
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16-bit Fibonacci LFSR with left-shift feedback and fixed max-length taps; parallel load supported.
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32-bit Fibonacci LFSR with enable, parallel load, and right-shift fixed max-length taps.
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64-bit LFSR with parameter TAP_SEL choosing between two fixed tap sets, plus load and enable.
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8-bit Fibonacci LFSR with parallel load and right-shift feedback via mask XOR for max-length taps.
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8-bit Galois LFSR with parallel load/shift enables using polynomial x^8+x^6+x^5+x^4+1.
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An 8-bit parallel scrambler using an LFSR to XOR input data with a pseudo-random sequence for data whitening.
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A 16-bit Additive Lagged Fibonacci pseudo-random number generator with taps j=3 and k=5.
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CRC-16-CCITT Serial
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Byte-serial CRC-32 generator with Ethernet-style polynomial, init 0xFFFFFFFF, and zlib-compatible output.
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A SystemVerilog module that checks incoming data against a PRBS32 sequence generated by an LFSR. It counts bit errors and asserts a persistent error flag.
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A 32-bit Pseudo-Random Binary Sequence generator using the IEEE 802.3 polynomial. Supports synchronous reset, enable control, and seed reload for deterministic testing.
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A latch-free 32-bit pseudo-random number generator implementing the Marsaglia xorshift algorithm with synchronous seed load and asynchronous reset.
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64-bit Xorshift pseudo-random number generator with seed loading and enable control.