Bus Interfaces

IP blocks

• AHB-Lite Simple Master systemverilogsimsyn

  A simple AHB-Lite master controller for SystemVerilog designs supporting single-cycle transactions.

• AHB-Lite Single-Beat Master systemverilogsimsyn

  Minimal AHB-Lite master that issues one read or write transfer per request.

• AHB-Lite Slave Interface systemverilogsimsyn

  Single-beat AHB-Lite slave with configurable address range, combinational read response, and write capture on full-word granularity.

• APB3 Master (Single-Transaction Pipeline) systemverilogsimsyn

  APB3 master with setup/access phases and one outstanding transaction.

• APB3 Master with Burst Support and Backpressure Handling systemverilogsimsyn

  A fully compliant APB3 master controller supporting single and burst transactions with auto-increment and backpressure handling.

• APB3 Slave Register Interface systemverilogsimsyn

  Configurable APB3 slave with word-aligned register file, byte-lane writes, and zero-wait-state PREADY.

• AXI-Lite 4-Register Bank systemverilogsimsyn

  A SystemVerilog IP core implementing a slave AXI-Lite interface with a 4-register bank and byte strobe support.

• AXI-Stream Register Slice verilogsimsyn

  Single-stage AXI-Stream register slice with backpressure support and forward/reverse ready pipelining.

• AXI-Stream Skid Buffer verilogsimsyn

  Single-entry skid buffer for AXI-Stream interfaces to handle backpressure.

• AXI4-Lite Simple Master (Single Beat) systemverilogsimsyn

  AXI4-Lite Simple Master (Single Beat)

• AXI4-Lite Simple Slave verilogsimsyn

  A basic AXI4-Lite slave module implementing a 4x32-bit register file with standard handshake protocols.

• Wishbone B3 Single-Beat Master systemverilogsimsyn

  Wishbone B3 master for classic single-beat read/write transactions.

• Wishbone B3 Slave (32-Bit, Single-Cycle) systemverilogsimsyn

  32-bit Wishbone B3 slave with combinational ack and a small register file.

• Wishbone B3 Slave (4 × 32-Bit Registers) verilogsimsyn

  Wishbone B3 slave exposing four 32-bit registers with ack on every cycle.

• Wishbone B3 to AHB-Lite Simple Bridge verilogsimsyn

  Converts Wishbone B3 master transactions into AHB-Lite master transactions for single-word transfers.

• Wishbone Byte-Strobe Slave 8 verilogsimsyn

  A Wishbone B.4 compliant slave module with byte-strobe support and a 256-byte internal memory map.

• Wishbone Simple Master verilogsimsyn

  A basic Wishbone B4 Simple Master supporting single-cycle Read and Write transactions with byte masking.

• Wishbone Slave 4-Register File verilogsimsyn

  A simple Wishbone slave module implementing a 4-register file with 32-bit data width and classic timing.

• Wishbone to Simple CSR Bridge verilogsimsyn

  Single-cycle Wishbone B3 slave bridging to a configurable array of 32-bit CSRs with byte-select write support.

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