Pro catalog
Clock Generators
Clock dividers, gating, and clock distribution helpers.
Category overview
Clock dividers, gating, and clock distribution helpers.
IP blocks
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A free-running 16-bit phase accumulator for Direct Digital Synthesis (DDS) with synchronous enable and asynchronous reset.
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A simple toggle flip-flop that divides the input clock frequency by two.
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A synchronous 4-phase one-hot clock-enable sequencer with enable gating and active-low reset.
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Asserts clock enable for N cycles on start pulse, ignoring subsequent starts during active burst.
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Generates a single-cycle clock enable pulse every N clock cycles when enabled.
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A configurable clock-enable divider that generates a single-cycle pulse every N input clock cycles, gated by an input enable signal.
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Stretches a 1-cycle CE pulse into N consecutive CE pulses without gating the clock.
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A divide-by-3 clock generator that produces a 50% duty cycle output using a 2-bit state machine.
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Captures input data on both rising and falling edges of a clock signal for DDR applications.
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Synthesizable fractional clock divider using phase accumulation for low jitter.
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Generates a clock enable signal with a fractional duty cycle M/N using a Bresenham accumulator.
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Glitch-free clock selector using clock-enable multiplexing
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Parameterized integer clock divider with 50% duty cycle supporting even divisors from 2 to 255.
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Detects when a monitored clock stops toggling for N reference cycles.
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Generates a periodic clock enable signal with configurable period N.
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Converts an asynchronous pulse signal into a toggled clock output synchronized to a reference clock.