Pro catalog
Multiplexers
Multiplexers, demultiplexers, and data-path selectors.
Category overview
Multiplexers, demultiplexers, and data-path selectors.
IP blocks
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A 4-to-1 priority multiplexer that selects data based on a one-hot select signal, where the lowest index bit has the highest priority.
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Combinational 16:1 mux with sixteen 32-bit inputs and a 4-bit select.
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Latch-free combinational 32-bit 2:1 mux with no clock, reset, or enable.
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Combinational 4:1 mux with four 3-bit inputs and a 2-bit select.
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Combinational 4:1 mux with 8-bit inputs; active-high enable forces zero output.
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Combinational 8:1 mux selecting one of eight 32-bit words when enabled.
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A glitch-free 2:1 clock multiplexer that synchronizes selection signals to prevent output glitches during clock source switching.
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Combinational multiplexer that selects one of 8 inputs based on a one-hot select signal, outputting zero for illegal codes.
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Registered 2:1 mux with packed 2-bit din bus, active-high enable, and active-low reset.
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Registered 16:1 mux with active-low enable and synchronous capture on clk.
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Canonical registered 2:1 lesson IP — synchronous 8-bit mux with enable and active-low reset.