Pro catalog
Control & Timers
FSMs, timers, watchdogs, and control/state sequencing blocks.
Category overview
FSMs, timers, watchdogs, and control/state sequencing blocks.
IP blocks
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A configurable 1 MHz tick generator module with synchronous reset and single-cycle pulse output.
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Reloadable 16-bit down counter that asserts match on countdown-to-zero and also when load writes zero.
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A 16-bit programmable prescaler that divides the input clock frequency by (prescale + 1).
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A 16-bit programmable timer module with configurable prescaler, up/down counting, and interrupt generation capabilities.
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Glitch-free 16-bit PWM with shadow registers for dynamic period/duty updates, active-high output, and full verification.
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A 32-bit down-counter interval timer that generates an interrupt request upon expiration, supporting preload, enable, and acknowledge signals.
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A 32-bit watchdog timer with kick reload, runtime timeout reprogramming, and configurable reset pulse width.
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Reloadable 8-bit down counter that pulses match_flag for one cycle when the count reaches zero.
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Filters glitches on an 8-bit input bus by requiring STABLE_CYCLES consecutive unchanged samples before updating dout.
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Combinational 8-bit window comparator that checks if data falls within an inclusive [lo, hi] range.
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Eight-channel 16-bit PWM with global period, per-channel duty, edge/center-aligned modes, and a simplified APB-like register interface.
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Sticky flag set on N-clock idle, cleared on activity pulse.
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An 8-bit bang-bang thermostat controller with hysteresis for heating control.
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Generates complementary drive signals with programmable dead-time to prevent shoot-through in half-bridge configurations.
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Measures duty cycle from period and high-count inputs using 8-bit fixed-point arithmetic.
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An 8-bit synchronous frequency counter that counts rising edges of an input signal only when a gate enable signal is active.
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An 8-bit Schmitt trigger with hysteresis for noise-immune digital signal processing.
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A synchronous 8-bit linear ramp generator that counts from 0 to a configurable target value.
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Asserts alarm if no input pulse is detected within timeout cycles.
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Generates a fixed-width output pulse in response to a trigger input, ignoring subsequent triggers during the active pulse.
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A programmable one-shot timer that freezes the countdown when the 'hold' signal is asserted.
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Measures the period of a periodic input signal in clock cycles using an 8-bit counter and FSM.
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A retriggerable one-shot pulse generator with configurable timeout duration.
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Moore Machine FSM cycling through Green, Yellow, and Red states triggered by a synchronous tick pulse.
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Saturating up/down counter with fixed 8-bit limits and boundary flags.