Pro catalog
Counters
Up/down, modulo, and loadable binary counters with enable logic.
Category overview
Up/down, modulo, and loadable binary counters with enable logic.
IP blocks
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A 16-bit cycle counter with an 8-bit prescaler for configurable clock division and carry output.
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Synchronous 4-digit BCD counter with up/down control, load, and carry/borrow flags.
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An 8-bit binary up counter with synchronous active-low reset and enable control.
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An 8-bit Johnson Counter (Twisted Ring) with synchronous reset and enable, implemented in Verilog.
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An 8-bit combinational leading zero counter that outputs the count of consecutive zeros from the MSB.
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An 8-bit ring counter with synchronous load and circular right shift functionality.
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An 8-bit up/down counter with synchronous load and asynchronous reset.
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Synchronous 4-bit bidirectional counter with enable and direction control.
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A 4-bit synchronous decade BCD counter that counts 0-9 with enable control and rollover pulse generation.
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An 8-bit synchronous counter with two independent compare-match outputs for event generation.
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16-bit event counter with rising-edge detection and synchronous capture register.
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An 8-bit Gray-code counter that converts an internal binary count to Gray code output, ensuring single-bit transitions between states.
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A fully synthesizable 4-bit up counter with synchronous load, enable, and asynchronous reset capabilities.
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An 8-bit loadable down counter with synchronous load, enable, and zero flag assertion. Wraps from 0 to 7 on underflow.
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A parameterized modulo-N counter with asynchronous reset and terminal count output.
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A synthesizable, parameterized synchronous counter with enable, asynchronous reset, and configurable wrap value.
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An 8-bit counter that wraps at 0xFF and sets a sticky overflow flag upon wrapping. The flag clears only on reset or clear.