RTL Studio runs Yosys as WebAssembly so you can synthesize Verilog / SystemVerilog in the tab, inspect netlists, and explore block / FSM / schematic views — without installing a desktop EDA suite.
Open the IDE: rtlstudio.dev · Product home: /home/ · SGDH portal: semisgdh.com
Quick workflow
- Open RTL Studio with a synthesizable design (examples under Tutorial / Welcome).
- Set the correct top module for synthesis.
- Run Synthesize (Yosys). Review the log for hierarchy / elaboration errors.
- Open netlist / diagram viewers from the synthesis results panel when available.
- On Pro, select foundry mapping such as SkyWater sky130 when you need liberty-backed cells (see in-app library picker).
Pair with /guides/verilog-simulation/ when you want sim → synth in one workspace.
What you can do
- Generic technology mapping on Free for teaching and early RTL exploration.
- SkyWater sky130 (and related Pro libraries) when your plan includes foundry mapping.
- Inspect synthesis output alongside lint (Slang) and simulation (Verilator) in the same IDE.
- Keep day-to-day synth local-first in the browser unless you opt into cloud features.
Free vs Pro libraries
| Tier | Synthesis |
|---|---|
| Free | Yosys generic mapping suitable for learning and many tutorial designs |
| Pro | Additional libraries such as SkyWater sky130; gated in the IDE when not entitled |
Billing and plan details live in-app (Profile → Plan) and in the Terms.
Limits (be honest with the tool)
- Browser Yosys is for education, labs, and early exploration — not a drop-in replacement for vendor P&R, timing closure, or tapeout sign-off.
- Very large designs may hit browser memory or time limits; start with the shipped examples.
- Cell mapping quality depends on the selected liberty / library pack.
Tips
- Synthesize a small counter or UART example first (counter, UART TX).
- Fix Slang lint / sim issues before chasing synth-only hierarchy errors.
- Use /learn/ for structured HDL tracks that complement synth labs.
FAQ
Do I need to install Yosys locally?
No. RTL Studio loads Yosys as WASM in your browser for the in-app Synthesize action.
Why is sky130 unavailable?
SkyWater sky130 mapping is a Pro library. Free users still get generic Yosys mapping. Sign in and check Profile → Plan if you expect Pro.
Does synthesize upload my design?
Standard synthesize stays local-first. Cloud upload happens only for explicit save/share. See Privacy.
Can I tape out from the browser netlist alone?
No. Treat browser synthesis as a learning and exploration step. Production ASIC/FPGA flows need vendor toolchains and sign-off.
Related reading
- /guides/verilog-simulation/ — dump VCD and waveforms
- /about/ — engines overview
- semisgdh.com — Design Study courses and free browser tools