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Verilog simulation in the browser

Run Verilog and SystemVerilog simulation in your browser with RTL Studio: Verilator WASM, $dumpfile/$dumpvars, VCD waveforms, and a practical FAQ.

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RTL Studio runs a SystemVerilog / Verilog simulator in your browser with WebAssembly — no desktop Verilator install for day-to-day labs. Use this guide to dump VCD, open waveforms, and fix empty-wave issues.

Open the IDE: rtlstudio.dev · Product home: /home/ · SGDH portal: semisgdh.com

Quick workflow

  1. Open RTL Studio and load an example (Welcome hub or Tutorial), or start from Quick start.
  2. Confirm your testbench calls $dumpfile("…") and $dumpvars (paths such as sim/dump.vcd are common in shipped examples).
  3. Run Simulate. Watch the terminal / Problems panel for compile or runtime errors.
  4. When a VCD appears in the workspace, open it in the Waveform editor (Surfer-based UI).
  5. Iterate: edit RTL or TB → lint (Slang) → simulate again.

For curriculum tracks, see /learn/.

What you can do

  • Edit Verilog / SystemVerilog and catch issues with Slang before you simulate.
  • Run an in-browser Verilator pipeline (timing / trace support on the product toolchain) and export VCD.
  • Inspect waveforms in the same tab; embed WaveDrom / Mermaid in project READMEs when documenting results.
  • Keep source local-first during standard edit → lint → sim (cloud save/share only when you opt in).

VCD rules that matter

  • Surfer and the workspace only update when simulation actually produces a VCD string. RTL Studio does not invent heuristic waveforms.
  • If $dumpfile / $dumpvars are missing, the run may succeed for $display but leave the waveform empty.
  • Put dumps in the active workspace path your example expects (see each example README).

Engines (short)

Path Notes
Verilator (WASM / A+ pipeline) Primary in-browser SV/Verilog sim for RTL Studio product flows
Icarus (where enabled) Used in some SGDH / legacy browser tool paths; see SGDH Verilog Simulator docs
Pro vs Free Core simulate remains available on Free; some engines and libraries are Pro-gated in the app UI

Tips

  • Start with Hello simulation to verify $display, then Quick start for a full dump → waveform loop.
  • Prefer one active workspace; keep TB and DUT files in the same project tree.
  • If Surfer looks blank after a successful run, re-open the VCD file or run Simulate once more after the viewer finishes loading.

FAQ

Why is the waveform empty?

Usually the testbench never dumped waves, the dump path does not match the file you opened, or the Surfer panel is still loading. Confirm $dumpfile / $dumpvars, check the terminal for “VCD”, then open the generated .vcd from the explorer.

Does simulation send my RTL to a server?

Standard Simulate stays local-first in the browser (WASM). Source is uploaded only if you explicitly use cloud save or share. See the Privacy Policy.

Is this the same as a foundry tapeout simulator?

No. Browser sim is excellent for learning, labs, and early RTL debug. It does not replace vendor timing, SDF, or sign-off flows.

Free vs Pro for simulation?

Core edit and simulate run on Free. Pro unlocks additional lectures, Open IP, and some engine/library features shown as Pro-only in the IDE. Details: /home/#faq.

Where can I learn more?