# Hello simulation

## What You Will Learn

Confirm the simulation toolchain with the smallest possible design: a module that prints `hello world` and exits. No clocks or ports required.

## Theory

An `initial` block runs once at time zero. `$display` writes to the simulator log; `$finish` ends the run. The testbench still sets up `sim/dump.vcd` like every later example.

## Files

| File | Role |
|------|------|
| `tb/tb.v` | Testbench — **`tb`** |
| `rtl/hello.v` | RTL / DUT — **`hello`** |

## Practice Architecture

```mermaid
flowchart TB
  tb[tb] --> hello[hello]
```

## What to explore

- Read the Simulation log and confirm `hello world`.
- Open the Waveform viewer — note how few signals exist.

## Expected Results

Simulation log contains: `hello world`

## Summary

A minimal health check: if hello simulation fails, fix the environment before debugging larger designs.

# Appendix (Code Review)

This section is an optional deep dive into the example source files. Line numbers refer to the copies in your workspace under `rtl/` and `tb/`.

## rtl/hello.v

**Purpose:** Zero-port smoke-test module that prints once and exits.

Lines 6–11 — Module `hello`

```verilog
module hello;
  initial begin
    $display("hello world");
    $finish;
  end
endmodule
```

**Code review:** The `initial` block is simulation-only: `$display` prints the greeting, then `$finish` stops the run. There are no ports, clocks, or synthesizable logic.

## tb/tb.v

**Purpose:** Testbench `tb` — elaborates `hello` and captures waves under `sim/`.

Lines 7–14 — Module `tb`

```verilog
`timescale 1ns/1ps
module tb;
  hello u_hello ();

  initial begin
    $dumpfile("sim/dump.vcd");
    $dumpvars(0, tb);
  end
endmodule
```

**Code review:** `tb` instantiates `hello`. Look for `$dumpfile` / `$dumpvars` in an `initial` block and any loops or `$display` checks that report PASS/FAIL.

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