Even correct boolean logic fails if it is late or asynchronous to its sampler. This section covers the two everyday concerns: synchronous timing inside one clock, and clock-domain crossing (CDC) between clocks.
Two different problems
| Problem | Domain | Failure mode |
|---|---|---|
| Setup / hold | Same clock | Wrong value captured; intermittent |
| CDC | Different clocks | Metastability, lost pulses, incoherent buses |
Topics in this section
- Setup & hold — edge-relative windows
- Clock-domain crossing — synchronizers & handshakes
RTL Studio angle
Browser sim (Verilator) does not replace STA. Use sim for functional intent; treat timing/CDC as design discipline you still apply when writing RTL — especially async inputs, multi-clock testbenches, and gray/FIFO patterns.