Sequential logic

Sequential logic remembers past values. In synchronous RTL, that memory is almost always edge-triggered flip-flops sharing a common clock.

Why clocks

A clock defines when state may change. Between edges, combinational logic settles. That contract is what setup & hold timing analysis enforces.

Canonical split

Most readable designs separate:

1. Next-state / next-data combo — always_comb computes *_next
2. State update — always_ff @(posedge clk) samples into flops

always_comb begin
  q_next = q;
  if (en) q_next = d;
end

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) q <= '0;
  else        q <= q_next;
end

Topics in this section

• Flip-flops — storage elements & enables
• Registers — vectors, pipelines, enables
• Counters — counting patterns

See also

• FSM — control as registered state
• Reset strategy