Combinational logic

Combinational logic computes outputs from current inputs only. There is no clocked memory: when inputs change, outputs update after propagation delay.

Mental model

In Verilog / SystemVerilog, combinational blocks are usually:

• Continuous assigns: assign y = a & b;
• always_comb / always @(*) with blocking (=) assignments

Design checklist

1. Every output path must be assigned in every branch (avoid unintended latches).
2. Prefer always_comb over sensitivity-list typos.
3. Keep combo cones readable — extract helpers / functions for repeated expressions.
4. Do not sample with a clock inside a combo process.

Topics in this section

• Gates — boolean primitives
• Mux & demux — select paths
• Arithmetic — adders, compare, signedness

See also

• Synthesizable RTL
• Setup & hold — why combo delay still matters on clocked paths