Wiki Finite state machines State encoding

State encoding

Binary, one-hot, and gray encoding trade-offs.

How states map to flop bits affects area, timing, and illegal-state behavior.

Common encodings

Encoding	Bits (N states)	Strengths	Watch-outs
Binary	`⌈log2 N⌉`	Compact	Next-state logic denser; illegal codes
One-hot	N	Fast decode; easy illegal detect	More flops
Gray	`⌈log2 N⌉`	Single-bit change on some arcs	Not all graphs are gray-friendly

typedef enum logic [1:0] {
  ST_IDLE = 2'd0,
  ST_RUN  = 2'd1,
  ST_DONE = 2'd2
} state_t;

In SystemVerilog, enum + unique case is the usual readable form. Synthesis may re-encode unless you force a style.

Illegal states

After reset release or SEU, the machine might land off-map. Options:

default next-state → ST_IDLE
Explicit illegal → error / reopen handshake
One-hot: detect !$onehot(state)

Safe defaults

For teaching and most FPGA RTL:

Use enum with explicit values you understand.
Always write a default in next-state and output cases.
Don’t optimize away recovery paths until you measure.

Tool notes

Yosys / vendor synthesizers can choose encodings via attributes or FSM extraction. If you need a guaranteed encoding (protocol analyzers, formal), set it explicitly and verify in the netlist or with assertions.