RTL Studio

Cannot run Monaco Editor from a file:// URL. Browsers block web workers on local files. Start a small HTTP server in the project folder, then open the http:// address.

cd /path/to/RTLStudio && python3 serve_coi.py

(serve_coi.py adds cross-origin isolation headers useful for WASM.) Or: python3 -m http.server 8080. Then visit http://127.0.0.1:8080/ (use 127.0.0.1, not file://).

Time

Raw lint logs

Open Tutorial or Open IP on the activity bar and pick a design — notes for that block and the tool flow appear in the Docs tab here.

No problems have been detected in the workspace.

[info] RTL Studio loaded.
[info] Open this Log tab to see Vim / extension messages (they do not appear in python http.server output).

[lint] Run “Lint check” in the left sidebar to append tool output here (Slang / Yosys). Background Slang checks update Problems only.

Run simulation to see output here.

Summary

Run synthesis to populate summary.

Raw Log

Run synthesis to populate detailed synthesis logs here.

About RTL Studio

Browser HDL IDE · Verilog & SystemVerilog

RtlStudio runs simulation, synthesis, lint, and waveform tools as WebAssembly inside your browser tab. Your RTL stays on your machine for compile and sim — nothing is sent to our servers unless you explicitly save to a cloud slot or share a link.

Principles

Auto-install WASM — open a tab, nothing to set up yourself
Unlimited sim, synthesis, and lint runs on your CPU
Monaco editor with HDL syntax highlighting
Resizable workbench: explorer, panels, editor splits

Engines (WASM)

Icarus Verilog — Verilog simulation
Verilator — SystemVerilog sim (Pro)
Yosys + SkyWater 130nm — synthesis & PPA
Slang & Verible — lint
Surfer & WaveDrom — VCD & timing diagrams

Workbench panels

Explorer: Multi-file workspaces, top module & testbench selection
Simulation: Icarus or Verilator runs, VCD output, coverage view
Synthesis: Yosys netlist, block / FSM / schematic viewers
Lint: Slang worker, Problems panel with jump-to-line
Waveform editor: Surfer VCD UI and WaveDrom authoring
Tutorial & Lecture: Examples and curriculum tracks — Verilog free; SV / UVM / AXI Pro
Open IP: Reference RTL blocks with packaged results — Pro

Account & cloud

Optional Google sign-in for cloud workspace slots (Free: 3 · Pro: 10), lecture progress, and subscription sync.

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Funding round · Founding price

Upgrade to RtlStudio Pro

Browser-native EDA — unlimited simulation and synthesis in your tab, with your source code never leaving your machine.

Founding member

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$239 $77 / year

List price $239/yr — your rate now while founding slots last.

Lock in $77/yr today. After this funding round, new Pro members start at $99/yr (list $239/yr).

Price lock: Stay subscribed and keep this annual rate. Cancel and resubscribe later at then-current pricing.

Secure checkout opens in a new tab via Lemon Squeezy (Merchant of Record). Billed annually; cancel anytime.

Free vs Pro

One paid plan — Pro. We keep shipping new tools and panels; subscribers get them without upgrading to another tier.

Feature	Free	Pro Recommended
Simulation / synthesis / lint runs	Unlimited (browser WASM)	Unlimited (browser WASM)
RTL source stays on your device	✓	✓
Cloud workspace slots	3	10
Tutorials & examples	✓	✓
Verilog lecture track	✓	✓
Open IP reference blocks	—	✓
All lecture tracks (SV, UVM, AXI)	—	✓
Verilator SystemVerilog simulation	—	✓
Future extensions (new tools & Lectures)	—	✓

Why RtlStudio Pro is different

Unlimited runs — no daily caps

Sim, synthesis, and lint compile in your browser via WebAssembly. No shared-server queues and no per-day run limits like cloud-hosted IDEs.

Your code never uploads for compile

Server-based flows must receive your RTL to run tools. RtlStudio keeps workspaces local to your tab — better for NDAs, employers, and tape-out IP.

Premium curriculum + Open IP

Pro unlocks packaged reference IPs, SystemVerilog / UVM / AXI masterclasses, and full Verilator simulation for real SV testbenches.

One plan — features keep growing

RtlStudio Pro is our only subscription. New WASM engines, workbench extensions, and lectures land in Pro as we ship — no second tier to buy later.

Frequently asked questions

Is there a free trial for Pro?

No. RtlStudio does not offer a multi-month Pro trial. You can use Free tier tutorials and the Verilog lecture track at no cost; Pro is a paid annual subscription when you need Open IP and advanced lectures.

Can I cancel anytime?

Yes. Cancel from your Lemon Squeezy customer portal or contact billing support. You keep Pro access until the end of your current annual billing period.

What is your refund policy?

Initial purchases include a 7-day money-back guarantee only if you have not accessed premium assets (Open IP, Pro lectures, and related libraries). Opening those assets waives the refund guarantee per our Terms. Renewals are not refundable. Refunded accounts cannot repurchase Pro.

What does “lifetime price lock” mean?

Your founding or launch annual rate applies for as long as you remain subscribed without a long lapse. If you cancel and subscribe again later, you pay the then-current public price.

Why is simulation unlimited?

Verilator, Yosys, Slang, and related tools run as WebAssembly inside your browser tab. Workloads execute on your CPU — we are not metering shared cloud compile minutes.

What are “future extensions”?

RtlStudio has one paid plan. As we add new browser-native tools, panels, and curriculum, Pro subscribers get access — there is no separate Pro Plus or add-on tier. Free stays on today’s feature set.

Manage subscription

Cancel RtlStudio Pro?

We'll be sad to see you go. If you cancel, you keep full Pro access until the end of your current annual billing period.

Pro stays active until your billing period ends.

Price lock ends: If you cancel, you won't be able to resubscribe at your current annual rate. Future sign-ups use then-current public pricing.

What you'll lose

Feature	Free	Pro
Simulation / synthesis / lint runs	Unlimited (browser WASM)	Unlimited (browser WASM)
RTL source stays on your device	✓	✓
Cloud workspace slots	3	10
Tutorials & examples	✓	✓
Verilog lecture track	✓	✓
Open IP reference blocks	—	✓
All lecture tracks (SV, UVM, AXI)	—	✓
Verilator SystemVerilog simulation	—	✓
Future extensions (new tools & Lectures)	—	✓

About RTL Studio

Principles

Engines (WASM)

Workbench panels

Account & cloud

Licenses

Site

Panels

Legal

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