# VCD → Waveform Editor

## What You Will Learn

Simulation produces VCD; the Waveform Editor can import and annotate those traces. `pulse_gen` is a compact FSM (`IDLE`/`RUN`/`DONE`) whose `busy` and `done` strobes make interesting wave shapes to practice the sim-to-editor workflow.

## Learning Objectives

- Follow `pulse_gen` states from `go` assertion through `done`.
- Relate FSM states to `busy` and `done` outputs.
- Open simulation VCD in the Waveform viewer and editor.
- Connect short sequential behavior to documentation timing diagrams.

## Theory

`pulse_gen` waits in `IDLE` until `go`, counts five cycles in `RUN` while `busy` is high, pulses `done` in `DONE`, then returns. This is a minimal handshake-shaped sequencer—similar to microcoded pulse generators in bring-up tests.

Exporting VCD to the Waveform Editor bridges RTL verification and communication with colleagues who may not re-run sim—timing sketches derived from real traces stay faithful to implemented behavior.

## When to use this pattern

Document interface timing from measured simulation when spec PDFs lag RTL—or when teaching students to read waves before drawing them by hand.

## Files

| File | Role |
|------|------|
| `tb/tb_pulse.v` | Testbench — **`tb_pulse`** |
| `rtl/pulse_gen.v` | RTL / DUT — **`pulse_gen`** |

## Practice Architecture

```mermaid
flowchart TB
  tb[tb_pulse] -->|clk rst_n go| dut[pulse_gen]
  dut -->|busy done| tb
```

## What to explore

- Plot `go`, `st`, `busy`, and `done` together after reset.
- Count cycles spent in `RUN` and match RTL `cnt == 3'd4` transition.
- Open the Waveform Editor with the generated VCD.
- Compare editor view to RTL state names.
- Sketch expected timing on paper, then verify against waves.

## Summary

Short FSM plus VCD export teaches the sim-to-diagram loop. `pulse_gen` is deliberately small so you focus on tooling, not complex datapath.

# Appendix (Code Review)

This section is an optional deep dive into the example source files. Line numbers refer to the copies in your workspace under `rtl/` and `tb/`.

## rtl/pulse_gen.v

**Purpose:** Three-state pulse FSM for VCD/editor practice (`pulse_gen`).

Lines 7–33 — Module `pulse_gen`

```verilog
`default_nettype none
module pulse_gen (
  input wire clk,
  input wire rst_n,
  input wire go,
  output wire busy,
  output wire done
);
  localparam [1:0] IDLE = 2'd0;
  localparam [1:0] RUN  = 2'd1;
  localparam [1:0] DONE = 2'd2;

  reg [1:0] st;
  reg [2:0] cnt;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      st <= IDLE; cnt <= 3'd0;
    end else case (st)
      IDLE: if (go) begin st <= RUN; cnt <= 3'd0; end
      RUN:  if (cnt == 3'd4) begin st <= DONE; cnt <= 3'd0; end
            else cnt <= cnt + 3'd1;
      DONE: st <= IDLE;
      default: st <= IDLE;
    endcase
  end
  assign busy = (st == RUN);
  assign done = (st == DONE);
endmodule
```

**Code review:** States: `IDLE`, `RUN`, `DONE` as 2-bit locals. Sequence: `go` leaves idle; `RUN` counts 0..4; `DONE` returns to idle. Outputs: `busy = (st==RUN)`; `done = (st==DONE)`. Single always: Clocked `case` on `st` with async reset.

## tb/tb_pulse.v

**Purpose:** Testbench `tb_pulse` — elaborates `pulse_gen` and captures waves under `sim/`.

Lines 7–28 — Module `tb_pulse`

```verilog
`timescale 1ns/1ps
module tb_pulse;
  reg clk, rst_n, go, busy, done;
  pulse_gen u_dut (
    .clk(clk),
    .rst_n(rst_n),
    .go(go),
    .busy(busy),
    .done(done)
  );
  initial clk = 0;
  always #5 clk = ~clk;
  initial begin
    $dumpfile("sim/dump.vcd");
    $dumpvars(0, tb_pulse);
    rst_n = 0; go = 0;
    #22 rst_n = 1;
    @(posedge clk); go = 1;
    @(posedge clk); go = 0;
    repeat (16) @(posedge clk);
    $finish;
  end
endmodule
```

**Code review:** `tb_pulse` instantiates `pulse_gen`. Look for `$dumpfile` / `$dumpvars` in an `initial` block and any loops or `$display` checks that report PASS/FAIL.

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