# Starter — TB + DUT

## What You Will Learn

RTL Studio's **initial project template**. This example teaches the workspace layout—`rtl.f`, `tb.f`, `rtl/design.v`, and `tb/testbench.v`—and how to run **lint**, **simulation**, **waveforms**, and **synthesis** once end to end.

The shipped `design.v` is placeholder RTL so the tools have something to compile. **Replace it with your own DUT** (any module you like) and update the testbench instance to match.

## Learning Objectives

- Know which tools read `rtl.f` vs `tb.f` and what each file list declares.
- Treat `rtl/design.v` as synthesizable DUT and `tb/testbench.v` as simulation-only harness.
- Set **Top module** and **Testbench** in the sidebars before lint, sim, and synth.
- Swap in your own RTL while keeping the same filenames and file-list pattern.

## Project layout

| File | Role |
|------|------|
| `rtl.f` | **DUT file list** — read by **Lint** and **Synthesis** |
| `tb.f` | **Simulation file list** — includes DUT via `-f rtl.f`, then the testbench |
| `rtl/design.v` | **DUT** — synthesizable RTL you own and may replace |
| `tb/testbench.v` | **Testbench** — clocks, reset, VCD dump, `$finish`; not synthesized |

### `rtl.f`

One path per line, relative to the workspace root. Lines starting with `#` are comments. Only files listed here are linted and synthesized. This starter lists a single DUT file:

```text
rtl/design.v
```

Add more RTL paths when your DUT spans multiple files.

### `tb.f`

Simulation elaborates everything in this list. `-f rtl.f` pulls in all DUT sources, then the testbench is appended:

```text
-f rtl.f
tb/testbench.v
```

Keep the testbench **after** the DUT so it can instantiate modules defined above.

### `rtl/design.v`

Your **design under test**. Lint and synthesis compile this file (via `rtl.f`). The default module is a small clocked block so the workflow works out of the box—you may rename the module, rewrite the logic, or paste in an entirely different design. After edits, align port names in `testbench.v` and pick the new module as the synthesis **Top module**.

### `tb/testbench.v`

Module `tb` wraps the DUT: it generates `clk` and `rst_n`, instantiates the DUT, writes `sim/dump.vcd` with `$dumpfile` / `$dumpvars`, and stops with `$finish`. Select **`tb`** as the Simulation **Testbench**—not the DUT module.

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